AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 70

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

software reset). After a hardware or software reset and
before the ENRCV bit in the MAC Configuration Con-
trol register has been set, the Logical Address can be
accessed by setting the LOG ADDR bit in the Internal
Address Configuration register (REG ADDR 18) and
then by performing 8 reads or writes to the Logical
Address Filter. Once ENRCV has been set, the ADDR
CHG bit in the Internal Address Configuration register
must be set and be polled until it is cleared by the
MACE device before setting the LOGADDR bit and
before accessing of the Logical Address Filter is
allowed.
If the least significant address bit of a received
message is set (Destination Address bit 00 = 1), then
the address is deemed logical, and passed through the
FCS generator. After processing the 48-bit destination
address, a 32-bit resultant FCS is produced and
strobed into an internal register. The high order 6-bits
of this resultant FCS are used to select one of the 64-bit
positions in the Logical Address Filter (see diagram). If
the selected filter bit is a 1, the address is accepted and
the packet will be placed in memory.
The first bit of the incoming address must be a 1 for a
logical address. If the first bit is a 0, it is a physical
70
47
Destination Address
Received Message
1 0
1
Logical Address Match Logic
MATCH = 1:
MATCH = 0:
CRC
GEN
SEL
Am79C940
Packet Accepted
Packet Rejected
31
32-Bit Resultant CRC
address and is compared against the value stored in
the Physical Address Register at initialization.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message
may be intended for the node. It is the user’s responsi-
bility to determine if the message is actually intended
for the node by comparing the destination address of
the stored message with a list of acceptable logical
addresses.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is always
enabled provided the Disable Receive Broadcast bit
(DRCVBC in the MAC Configuration Control register) is
cleared. If the Logical Address Filter is loaded with all
zeroes (and PROM = 0), all incoming logical addresses
except broadcast will be rejected.
Multicast addressing can only be performed when
using external loopback (LOOP [1–0] = 0) by pro-
gramming RCVFCSE = 1 in the User Test Register.
The FCS logic is internally allocated to the receiver
section, allowing the FCS to be computed on the in-
coming logical address.
26
64
6
63
MUX
(LADRF)
Address
Logical
Filter
0
0
MATCH*
16235D-10