AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 65

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 3-1
Bit 0
FIFO Configuration Control
(FIFOCC)
All bits within the FIFO Configuration Control register
will be set to their default state upon a hardware or soft-
ware reset. Bit assignments are as follows:
Bit
Bit 7-6
XMTFW[1-0]
XMTSP [1–0]
XMTSP [1-0]
RES
SWRST
XMTFW
[1-0]
Name
RCVFW [1-0] XMTFWU RCVFWU
00
01
10
11
00
01
10
11
Transmit FIFO Watermarks
Transmit Start Point
Reserved. Read as zeroes. Al-
ways write as zeroes.
Software Reset. When set, pro-
vides an equivalent of the hard-
ware RESET pin function. All
register bits will be set to their
default values. The MACE de-
vice will require re-initialization
after SWRST has been activat-
ed. The MACE device will clear
SWRST during its internal reset
sequence.
Description
Transmit
FIFO
XMTFW
TDTREQ is asserted in relation
to the number of write cycles to
the Transmit FIFO. TDTREQ will
be asserted at any time that the
number of write cycles specified
by XMTFW can be executed.
XMTFW is set to a value of 00 (8
cycles)
software reset.
The XMTFW value will only be
updated when the XMTFWU bit
is set.
To ensure that sufficient space
is present in the XMTFIFO to
accept the specified number of
Watermark.
after
controls
XMTBRST
(REG ADDR 12)
Bytes
Bytes
112
XX
16
64
16
32
hardware
4
8
the
RCVBRST
point
Am79C940
or
Bit 5-4
Bit 3
XMTSP [1–0]
RCVFW
[1-0]
XMTFWU
00
01
10
11
Receive FIFO Watermarks
write
End-Of-Frame
TDTREQ may go inactive before
the XMTSP threshold is reached
when using the non burst mode
(XMTBRST = 0). The host must
be aware that despite TDTREQ
going inactive, additional space
exists in the XMTFIFO, and the
data write must continue to
ensure the XMTSP threshold is
achieved. No transmit activity
will commence until the XMTSP
threshold is reached. When
using the burst mode, TDTREQ
will not be de-asserted until only
a single write cycle can be per-
formed. See the FIFO Sub-sys-
tem section for additional de-
tails.
Receive FIFO Watermark.
RCVFW
RDTREQ is asserted in relation
to the number of bytes available
in the RCVFIFO. RCVFW speci-
fies the number of bytes which
must be present (once the pack-
et has been verified as a
non-runt), before the RDTREQ
is asserted. Note however that in
order for RDTREQ to be activat-
ed for a new frame, at least
64-bytes
received. This effectively avoids
reacting to receive frames which
are runts or suffer a collision dur-
ing the slot time (512 bit times).
If the Runt Packet Accept fea-
ture (RPA in Receive Frame
Control)
RDTREQ pin will be activated as
soon as either 64-bytes are
received, or a complete valid
receive
(regardless of length). RCVFW
is set to a value of 10 (64 bytes)
after hardware or software reset.
The RCVFW value will only be
updated when the RCVFWU bit
is set.
Transmit
Update. Allows update of the
cycles
frame
controls
must
is
FIFO
Bytes
enabled,
(including
XX
16
32
64
is
have
Watermark
the
delimiter),
detected
been
point
the
65
an