AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 68

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 0
PHY Configuration
Control (PHYCC)
All bits within the PHY Configuration Control register
with the exception of LNKFL, are cleared by hardware
or software reset. Bit assignments are as follows:
Bit
Bit 7
68
LNKFL DLNKTST REVPOL DAPC
PORTSEL
[1–0]
00
01
10
11
ENPLSIO
LNKFL
Name
PORTSEL Interface Definitio
Enable PLS I/O. ENPLSIO is
used to enable the optional I/O
functions from the PLS function.
The following pins are affected
by the ENPLSIO bit: RXCRS,
RXDAT,
TXDAT-,
RDCLK and SRD. Note that if an
external SIA is being utilized via
the GPSI, PORTSEL [1–0] = 11
must be programmed before
ENPLSIO is set, to avoid con-
tention of clock, data and/or
carrier indicator signals.
Description
Link Fail. Reports the link integ-
rity of the 10BASE–T receiver.
When the link test function is
enabled (DLNKTST = 0), the
absence of link beat pulses on
the RXD
integrated 10BASE–T transceiv-
er to go into the link fail state. In
the link fail state, data transmis-
sion, data reception, data loop-
back and the collision detection
functions
remain disabled until valid data
or >5 consecutive link pulses
appear on the RXD pair. During
link fail, the LNKFL bit will be set
and the LNKST pin should be
externally pulled HIGH. When
the link is identified as function-
al, the LNKFL bit will be cleared
and the LNKST pin is driven
LOW, which is capable of direct-
ly driving a Link OK LED. In
order to inter-operate with sys-
tems which do not implement
Link Test, this function can be
disabled
10BASE–T
Interface
DAI Port
Active
GPSI
AUI
LRT
are disabled,
pair will cause the
TXEN,
by
CLSN,
ASEL
(REG ADDR 15)
DXCVR Pin
RWAKE
setting
n
HIGH
HIGH
LOW
LOW
STDCLK,
TXDAT+,
AWAKE
and
the
Am79C940
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DLNKTST
REVPOL
DAPC
LRT
ASEL
RWAKE
DLNKTST bit. With Link Test
disabled (DLNKTST = 1), the
data driver, receiver and loop-
back functions as well as colli-
sion detection remain enabled
irrespective of the presence or
absence of data or link pulses on
the RXD pair. The transmitter
will continue to generate link
beat pulses during periods of
transmit data inactivity. Set by
hardware or software reset.
Disable Link Test. When set, the
integrated 10BASE–T transceiv-
er will be forced into the link pass
state, regardless of receive link
test pulses or receive packet
activity.
Reversed Polarity. Indicates the
receive polarity of the RD pair.
When normal polarity is detect-
ed, the REVPOL bit will be
cleared, and the RXPOL pin
(capable of driving a Polarity OK
LED) will be driven LOW. When
reverse polarity is detected, the
REVPOL bit will be set, and the
RXPOL pin should be externally
pulled HIGH.
Disable Auto Polarity Correction.
When set, the automatic polarity
correction
Polarity detection and indication
will still be possible via the
RXPOL pin.
Low Receive Threshold. When
set, the threshold of the twisted
pair receiver will be reduced by
4.5 dB, to allow extended dis-
tance operation.
Auto Select. When set, the
PORTSEL [1-0] bits are overrid-
den, and the MACE device will
automatically select the operat-
ing media interface port. When
the 10BASE–T transceiver is in
the link pass state (due to receiv-
ing valid packet data and/or Link
Test pulses or the DLNKTST bit
is set), the 10BASE-T port will be
used. When the 10BASE–T port
is in the link fail state, the AUI
port will be used. Switching
between the ports will not occur
during transmission in order to
avoid any type of fragment
generation.
Remote Wake. When set prior to
the SLEEP pin being activated,
the AUI and 10BASE–T receiver
sections and the EADI port will
will
be
disabled.