AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 80

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Missing Table Title?
SYSTEM APPLICATIONS
Host System Examples
Motherboard DMA Controller
The block diagram shows the MACE device interfacing
to a 8237 type DMA controller. Two external latches are
used to provide a 24 bit address capability. The first
latch stores the address bits A [15:8], which the 8237
will output on the data line DB [7:0], while the signal
ADSTB is active. The second latch is used as a page
register. It extends the addressing capability of the
8237 from 16–bit to 24–bit. This latch must be pro-
grammed by the system using an I/0 command to gen-
erate the signal LATCHHIGHADR.
The MACE device uses two of the four DMA channels.
One is dedicated to fill the Transmit FIFO and the other
to empty the Receive FIFO. Both DMA channels
should be programmed in the following mode:
Note:
This is the same configuration as used in the IBM PC.
80
29
30
31
Addr
— Command Register:
Memory to memory disabled
DREQ sense active high
DACK sense active low
Normal timing
Late Write
Mnemonic
UTR
–
–
80
40
20
10
08
06
Reserved
Reserved
User Test Register
RCVFCSE
RTRE
RTRD
RPA
FCOLL
LOOP
00
01
10
11
01
Reserved Test Register Enable–must be 0
Reserved Test Register Disable
Runt Packet Accept
Force Collision
Receive FCS Enable
Loopback control (2 bits)
No loopback
External loopback
Internal loopback, excludes MENDEC
Internal loopback, includes MENDEC
–
Contents
The 8237 and the MACE device run synchronous to
the same SCLK. The 8237 is programmed to execute
a transfer in three clock cycles This requires an extra
wait state in the MACE device during FIFO accesses.
A system not using the same configuration as in the
IBM PC can minimize the bus bandwidth required by
the MACE device by programming the DMA controller
in the compressed timing mode.
Care must be taken with respect to the number of
transfers within a burst. The 8237 will drive the signal
EOP low every time the internal counter reaches the
zero. The MACE device however only expects EOF as-
serted on the last byte/word of a packet. This means,
that the word counter of the 8237 should be initially
loaded with the number of bytes/words in the whole
packet. If the application requires that the packet will be
constructed from several buffers at transmit time, some
extra logic is required to suppress the assertion of EOF
at the end of all but the last buffer transferred by the
DMA controller. Also note that the DMA controller can
only handle either bytes or words at any time. It re-
quires special handling if a packet is transferred to the
MACE device Transmit FIFO in word quantities and it
ends in an odd byte.
The 8237 requires an extra clock cycle to update the
external address latch every 256 transfer cycles. This
example assumes that an update of the external
address latch occurs only at the beginning of the
block transfer.
R/W as 0
R/W as 0
R/W
R/W
R/W