AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 64

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 3
Bit 2
Bit 1
Bit 0
.
Poll Register (PR)
This register contains copies of internal status bits to
simplify a host implementation which is non-interrupt
driven. The register is read only, and its status is unaf-
fected by read operations. All register bits are cleared
by hardware or software reset. Bit assignments are as
follows:
Bit
Bit 7
64
XMTSV
TDTREQ
RNTPCOM Runt Packet Count Overflow
MPCOM
RCVINTM
XMTINTM
XMTSV
Name
RDTREQ
the MACE device regardless of
the state of the RCVCCO bit, if
RCVCCOM is set. It is cleared
by activation of the RESET pin
or SWRST bit.
Mask. RNTPCOM is the mask
for
Count Overflow). The INTR pin
will not be asserted by the
MACE device regardless of the
state of the RNTPCO bit, if
RNTPCOM is set. It is cleared by
activation of the RESET pin or
SWRST bit.
Missed Packet Count Overflow
Mask. MPCOM is the mask for
MPCO (Missed Packet Count
Overflow). The INTR pin will not
be asserted by the MACE device
regardless of the state of the
MPCO bit, if MPCOM is set. It is
cleared by activation of the
RESET pin or SWRST bit.
Receive
RCVINTM is the mask for
RCVINT. The INTR pin will not
be asserted by the MACE device
regardless of the state of the
RCVINT bit, if RCVINTM is set. It
is cleared by activation of the
RESET pin or SWRST bit.
Transmit
XMTINTM is the mask for
XMTINT. The INTR pin will not
be asserted by the MACE device
regardless of the state of the
XMTINT bit, if XMTINT is set. It
is cleared by activation of the
RESET pin or SWRST bit
Description
Transmit Status Valid. Transmit
Status Valid indicates that the
Transmit Frame Status is valid.
RES
RNTPCO
RES
(REG ADDR 10)
Interrupt
Interrupt
RES
(Runt
RES
Packet
Mask.
Mask.
RES
Am79C940
Bit 6
Bit 5
Bit 4-0
BIUConfigurationControl(BIUCC)
All bits within the BIU Configuration Control register will
be set to their default state upon a hardware or soft-
ware reset. Bit assignments are as follows:
Bit
Bit 7
Bit 6
Bit 5-4
RES
BSWP XMTSP [1-0]
TDTREQ
RDTREQ
RES
RES
BSWP
XMTSP
[1-0]
Name
Transmit
Request. An internal indication
of the current request status of
the Transmit FIFO. TDTREQ is
set when the external TDTREQ
signal is asserted.
Receive Data Transfer Request.
An internal indication of the cur-
rent
Receive FIFO. RDTREQ is set
when the external RDTREQ
signal is asserted.
Reserved. Read as zeroes.
Always write as zeroes.
Description
Reserved. Read as zero. Always
write as zero.
Byte Swap. The BSWP function
allows data to and from the
FIFOs to be orientated accord-
ing to little endian or big endian
byte
BSWP is cleared by by activa-
tion of the RESET pin or SWRST
bit, defaulting to Intel byte
ordering.
Transmit Start Point. XMTSP
controls the point preamble
transmission
relation to the number of bytes
written to the XMTFIFO. When
the entire frame is in the XMT-
FIFO (or the XMTFIFO becomes
full before the threshold is
achieved), transmission of pre-
amble will start regardless of the
value in XMTSP (once the IPG
time has expired). XMTSP is
given a value of 10 (64 bytes)
after hardware or software reset.
Regardless of XMTSP, the FIFO
will not internally over write its
data until at least 64 bytes, or the
entire frame, has been transmit-
ted onto the network. This
ensures that for collisions within
the slot time window, transmit
data need not be re-written to
the XMTFIFO, and re-tries will
be handled autonomously by the
MACE device.
RES
request
ordering
RES
Data
commences
status
(REGADDR11)
RES
conventions.
Transfer
SWRST
of
the
in