AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 58

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

of data in a transmit frame is being written to the
XMTFIFO, by asserting the EOF signal.
Transmit Frame Control (XMTFC)
The Transmit Frame Control register is latched inter-
nally on the last write to the Transmit FIFO for each in-
dividual packet, when EOF is asserted. This permits
automatic transmit padding and FCS generation on a
packet-by-packet basis.
Bit
Bit 7
Bit 6-4
Bit 3
58
DRTRY
Name
DRTRY
RES
DXMTFCS Disable Transmit FCS. When
RES
RES
DXMTFCS
Description
Disable Retry. When DRTRY is
set, the MACE device will pro-
vide a single transmission at-
tempt for the packet, all further
retries will be suspended. In the
case of a collision during the at-
tempt, a Retry Error (RTRY) will
be reported in the Transmit Sta-
tus. With DRTRY cleared, the
MACE device will attempt up to
15 retries (16 attempts total) be-
fore indicating a Retry Error.
DRTRY is cleared by activation
of the RESET pin or SWRST bit.
DRTRY is sampled during the
transmit
collision occurs. DRTRY should
not be changed whilst data
remains in the Transmit FIFO
since this may cause an unpre-
dictable retry response to a colli-
sion. Once the Transmit FIFO is
empty, DRTRY can be repro-
grammed.
Reserved. Read as zeroes.
Always write as zeroes.
DXMTFCS = 0 the transmitter
will generate and append an
FCS to the transmitted frame.
When DXMTFCS = 1, no FCS
will be appended to the transmit-
ted frame, providing that APAD
XMT is also clear. If APAD XMT
is set, the calculated FCS will be
appended to the transmitted
message regardless of the state
of DXMTFCS. The value of
DXMTFCS for each frame is
programmed when EOF is as-
serted to transfer the last byte/
word for the transmit packet to
the FIFO. DXMTFCS is cleared
by activation of the RESET pin
or SWRST bit. DXMTFCS is
sampled only when EOF is
RES
process
(REG ADDR 2)
RES
APAD XMT
when
Am79C940
a
Bit
Bit 2-1
Bit 0
Transmit Frame Status (XMTFS)
The Transmit Frame Status is valid when the XMTSV
bit is set. The register is read only, and is cleared when
XMTSV is set and a read operation is performed. The
XMTINT bit in the Interrupt Register will be set when
any bit is set in this register.
Note that if XMTSV is not set, the values in this register
can change at any time, including during a read opera-
tion. This register should be read after the Transmit
Retry Count (XMTRC). See the description of the
Transmit Retry Count (XMTRC) for additional details.
Bit
Bit 7
Bit 6
Bit 5
XMTSV
UFLO
RES
APAD XMT Auto Pad Transmit. APAD XMT
XMTSV
UFLO
LCOL
Name
Name
LCOL MORE
asserted during a Transmit FIFO
write.
Description
Reserved. Read as zeroes.
Always write as zeroes.
enables the automatic padding
feature. Transmit frames will be
padded to extend them to 64
bytes including FCS. The FCS is
calculated for the entire frame
including pad, and appended af-
ter the pad field. APAD XMT will
override the programming of the
DXMTFCS bit. APAD XMT is set
by activation of the RESET pin
or SWRST bit. APAD XMT is
sampled only when EOF is as-
serted during a Transmit FIFO
write.
Description
Transmit Status Valid. Transmit
Status Valid indicates that this
status is valid for the last frame
transmitted.
XMTSV will not change during a
read operation.
Underflow. Indicates that the
Transmit FIFO emptied before
the end of frame was reached.
The transmitted frame is truncat-
ed at that point. If UFLO is set,
TDTREQ will be de-asserted,
and will not be re-asserted until
the XMTFS has been read.
Late Collision. Indicates that a
collision occurred after the slot
time of the channel elapsed. If
LCOL is set, TDTREQ will be
de-asserted, and will not be
ONE
DEFER
The
(REG ADDR 3)
LCAR
value
RTRY
of