AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 95
![no-image](/images/no-image-200.jpg)
AM79C940JC/W
Manufacturer Part Number
AM79C940JC/W
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C940JCW.pdf
(144 pages)
- Current page: 95 of 144
- Download datasheet (2Mb)
AC CHARACTERISTICS (continued)
Note:
1. Not tested but data available upon request.
GPSI Clock Timing
GPSI Timing
EADI Feature Timing
No.
17
18
19
20
21
22
23
24
25
26
70
71
72
73
74
75
76
77
78
79
80
81
85
86
87
88
89
90
91
Parameter
t
Symbol
t
t
t
t
SFBDHIH
t
t
t
t
t
DSFBDR
t
t
t
t
t
DSFBDF
EAMRIS
t
EAMR
t
STDCH
STDCR
t
SRDCH
SRDCL
SRDCR
SRDCF
TXEND
TXENH
t
t
t
t
t
t
t
t
t
STDCL
STDCF
t
CLSHI
STDC
SRDC
TXDD
TXDH
RXDR
RXDF
RXDH
RXDS
t
CRSH
EAMS
EARS
CRSL
TXH
L
STDCLK period
STDCLK low pulse width
STDCLK high pulse width
STDCLK rise time
STDCLK fall time
SRDCLK period
SRDCLK HIGH pulse width
SRDCLK LOW pulse width
SRDCLK rise time
SRDCLK fall time
STDCLK delay to TXEN
TXEN hold time from STDCLK
STDCLK delay to TXDAT+ change (C
TXDAT+ hold time from STDCLK
RXDAT rise time
RXDAT fall time
RXDAT hold time (SRDCLK
RXDAT change)
RXDAT setup time (RXDAT stable
to SRDCLK )
RXCRS low time
CLSN high time
TXEN or TXDAT hold time from
CLSN
RXCRS hold time from SRDCLK
SRDCLK delay to SF/BD
SRDCLK delay to SF/BD
EAM/R invalid setup prior to
SRDCLK after SFD
EAM setup to SRDCLK at bit 6 of
Source Address byte 1 (match
packet)
EAM/R low time
SF/BD high hold from last
SRDCLK
EAR setup SRDCLK at bit 6 of
message byte 64
(reject normal packet)
Parameter Description
to
See Note 1
See Note 1
See Note 1
See Note 1
(C
(C
(C
See Note 1
See Note 1
See Note 1
L
L
L
L
Test Conditions
= 50 pF)
= 50 pF)
= 50 pF)
= 50 pF)
t
t
STDC
STDC
32*t
Min (ns)
–150
200
100
99
45
45
85
38
38
25
5
5
0
0
0
0
STDC
+ 20
+ 30
Max (ns)
96*t
101
115
70
70
20
20
5
5
5
5
8
8
STDC
95
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