AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 37

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

(1)
(2)
r ece pti on, re se t the i nte r Fr am e ga p ti mi ng i f
carrierSense becomes true during the first 2/3 of the
interFrame gap timing interval. During the final 1/3 of
the interval the timer shall not be reset to ensure fair
access to the medium. An initial period shorter than 2/
3 of the interval is permissible including zero.“
The MAC engine implements the optional receive two
p a r t d e f e r r a l a l g o r i t h m , w i t h a f i r s t p a r t i n -
ter-frame-spacing time of 6.0 s. The second part of
the inter-frame-spacing interval is therefore 3.6 s.
The MACE device will perform the two part deferral
algorithm as specified in Section 4.2.8 (Process Defer-
ence). The Inter Packet Gap (IPG) timer will start timing
the 9.6 s InterFrameSpacing after the receive carrier
i s d e -a s s e r t e d . D u r i n g t h e f i r s t p a r t d e f e r r a l
(InterFrameSpacingPart1-IFS1) the MACE device will
defer any pending transmit frame and respond to the
receive message. The IPG counter will be reset to zero
continuously until the carrier deasserts, at which point
the IPG counter will resume the 9.6 s count once
again. Once the IFS1 period of 6.0 s has elapsed, the
MACE device will begin timing the second part deferral
(InterFrameSpacingPart2-IFS2) of 3.6 s. Once IFS1
has completed, and IFS2 has commenced, the MACE
chip will not defer to a receive packet if a transmit
packet is pending. This means that the MACE device
will not attempt to receive an incoming packet, and it
will start to transmit at 9.6 s regardless of network
activity, forcing a collision if an existing transmission is
in progress. The MACE device will guarantee to com-
plete the preamble (64-bit) and jam (32-bit) sequence
before ceasing transmission and invoking the random
backoff algorithm.
In addition to the deferral after receive process, the
MACE device also allows transmit two part deferral to
be implemented as an option. The option can be dis-
abled using the DXMT2PD bit in the MAC Configura-
ti o n C o nt r o l r e g i s t er. Two p a r t d e fe r r a l a f te r
transmission is useful for ensuring that severe IPG
shrinkage cannot occur in specific circumstances,
causing a transmit message to follow a receive mes-
sage so closely, as to make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
erate the SQE Test message (a nominal 10 MHz burst
of 5-15 BT duration) on the CI pair (within 0.6-1.6 s
after the transmission ceases). During the time period
in which the SQE Test message is expected the MACE
device will not respond to receive carrier sense.
interpacket gap, as soon as transmitting and carrier
Sense are both false.
Upon completing a transmission, start timing the
When timing an interFrame gap following
Am79C940
The MACE device implements a carrier sense blinding
period within 0 s-4.0 s from deassertion of carrier
sense after transmission. This effectively means that
when transmit two part deferral is enabled (DXMT2PD
in the MAC Configuration Control register is cleared)
the IFS1 time is from 4 s to 6 s after a transmission.
However, since IPG shrinkage below 4 s will not be
encountered on correctly configured networks, and
since the fragment size will be larger than the 4 s
blinding window, then the IPG counter will be reset by
a worst case IPG shrinkage/fragment scenario and the
MACE device will defer its transmission. The MACE
chip will not restart the carrier sense blinding period if
carrier is detected within the 4.0-6.0 s portion of IFS1,
but will restart timing of the entire IFS1 period.
Contention Resolution (Collision Handling)
Collision detection is performed and reported to the
MAC engine either by the integrated Manchester
Encoder/Decoder (MENDEC), or by use of an external
function (e.g. Serial Interface Adaptor, Am7992B)
utilizing the GPSI.
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MACE de-
vice will complete the preamble/SFD before appending
the jam sequence. If a collision is detected after the
preamble/SFD has been completed, but prior to 512
bits being transmitted, the MACE device will abort the
transmission, and append the jam sequence immedi-
ately. The jam sequence is a 32-bit all zeroes pattern.
The MACE device will attempt to transmit a frame a
total of 16 times (initial attempt plus 15 retries) due to
normal collisions (those within the slot time). Detection
of collision will cause the transmission to be re-sched-
uled, dependent on the backoff time that the MACE de-
vice computes. Each collision which occurs during the
transmission process will cause the value of XMTRC in
the Transmit Retry Count register to be updated. If a
single retry was required, the ONE bit will be set in the
Transmit Frame Status. If more than one retry was re-
quired, the MORE bit will be set, and the exact number
of attempts can be determined (XMTRC+1). If all 16 at-
tempts experienced collisions, the RTRY bit will be set
See ANS t42I/IEEE Std 802.3-1990 Edition,
7.2.4.6 (1)):
opens a time window during which it expects to see
the signal_quality_error signal asserted on the
Control In circuit. The time window begins when the
CARRIER_STATUS becomes CARRIER_OFF. If
execution of the output function does not cause
CARRIER_ON to occur, no SQE test occurs in the
DTE. The duration of the window shall be at least
4.0 s but no more than 8.0 s. During the time win-
dow the Carrier Sense Function is inhibited.”
“At the conclusion of the output function, the DTE
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