AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 93

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same
between Commercial devices and Industrial devices.)
Notes:
1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge
2. Tested with C
3. Guaranteed by design–not tested.
4. t
Clock and Reset Timing
Internal MENDEC Clock Timing
BIU TIMING (Note 1)
1. 33
No.
12
13
14
31
32
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
of SCLK (SCLK ). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ).
vs. Load Chart.
11
1
2
3
4
5
6
7
9
DATD
is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.
Parameter
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLKH
SCLKR
SCLKF
t
t
t
t
t
t
t
t
SCLKL
t
t
DATIH
t
ADDS
ADDH
DTVD
DTVH
EOFD
EOFH
EOFS
EOFH
RDTD
RDTH
SCLK
t
t
t
SLVH
DATD
DATH
TDTD
TDTH
DATS
DATE
DATD
t
SLVS
CSIS
RST
t
t
X1H
X1R
X1F
X1L
L
BT
X1
set at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay
SCLK period
SCLK LOW pulse width
SCLK HIGH pulse width
SCLK rise time
SCLK fall time
RESET pulse width
Network Bit Time (BT)=2*tX1 or tSTDC
XTAL1 period
XTAL1 HIGH pulse width
XTAL1 LOW pulse width
XTAL1 rise time
XTAL1 fall time
Address valid setup to SCLK
Address valid hold after SCLK
CS or FDS and TC, BE1–0,
R/W setup to SCLK
CS or FDS and TC, BE1–0,
R/W hold after SCLK
Data out valid delay from SCLK
Data out valid hold from SCLK
DTV valid delay from SCLK
DTV valid hold after SCLK
EOF valid delay from SCLK
EOF output valid hold after SCLK
CS inactive prior to SCLK
EOF input valid setup to SCLK
EOF input valid hold after SCLK
RDTREQ valid delay from SCLK
RDTREQ input valid hold after SCLK
TDTREQ valid delay from SCLK
TDTREQ input valid hold after SCLK
Data in valid setup to SCLK
Data in valid setup after SCLK
Data output enable delay from SCLK (Note
3)
Data output disable delay from SCLK (Note
3, 4)
Parameter Description
C
C
C
C
C
L
L
L
L
L
= 100 pF (Note 2)
= 100 pF (Note 2)
= 100 pF (Note 2)
= 100 pF (Note 2)
= 100 pF (Note 2)
Test Conditions
0.4*t
0.4*t
Min (ns)
15*t
49.995
40
99
20
20
9
2
9
2
6
6
6
9
9
2
6
6
9
2
0
SCLK
SCLK
SCLK
Max (ns)
0.6*t
0.6*t
50.005
1000
101
32
32
32
32
32
25
5
5
5
5
SCLK
SCLK
93