AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 48

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

placing the appropriate address (00110b) on the
address bus and executing four read cycles (CS
active).
Either the FIFO Direct or Register Address modes can
be interleaved at any time to read the Receive Frame
Status, although this is considered unlikely due to the
additional overhead it requires. In either case, no addi-
tional data will be read from the RCVFIFO until the
Receive Frame Status has been read, as four bytes
appended to the end of the packet when using the
FIFO Direct mode, or as four bytes from the Receive
Frame Status location when using the Register
Address mode.
EOF will only be driven by the MACE device when
reading received packet data from the RCVFIFO. At all
other times, including reading the Receive Frame Sta-
tus using the FIFO Direct mode, the MACE device will
place EOF in a high impedance state.
RDTREQ should be sampled on the falling edge of
SCLK. The assertion of RDTREQ is programmed by
RCVFW, and the de-assertion is modified dependent
on the state of the RCVBRST bit (both in the FIFO Con-
figuration Control register). See the section Receive
FIFO Read for additional details.
Write Access
Details of the write access timing are located in the AC
Waveforms section, Host System Interface, figures:
Two-Cycle Transmit FIFO/Register Write Timing and
Three-Cycle Transmit FIFO/Register Write Timing.
Write cycles are executed in a similar manner as the
read cycle previously described, but with the R/W input
low, and the host responsible to provide the data with
sufficient set up to the falling edge of SCLK after S2.
After a FIFO write, TDTREQ should be sampled on or
after the falling (EDSEL = HIGH) edge of SCLK after
S3 of the FIFO write. The state of TDTREQ at this time
will reflect the state of the XMTFIFO.
After going active (low), TDTREQ will remain low for
two or more XMTFIFO writes.
The minimum high (inactive) time of TDTREQ is one
SCLK cycle. When EOF is written to the Transmit
FIFO, TDTREQ will go inactive after one SCLK cycle,
for a minimum of one SCLK cycle.
Initialization
After power-up, RESET should be asserted for a mini-
mum of 15 SCLK cycles to set the MACE device into a
defined state. This will set all MACE registers to their
default values. The receive and transmit functions will
be turned off. A typical sequence to initialize the MACE
device could look like this:
48
Am79C940
Write the BIU Configuration Control (BIUCC) regis-
ter to change the Byte Swap mode to big endian or
to change the Transmit Start Point.
Write the FIFO Configuration Control (FIFOCC)
register to change the FIFO watermarks or to
enable the FIFO Burst Mode.
Write the Interrupt Mask Register (IMR) to disable
unwanted interrupt sources.
Write the PLS Configuration Control (PLSCC)
register to enable the active network port. If the
GPSI interface is used, the register must be written
twice. The first write access should only set
PORTSEL [1–0] = 11. The second access must
write again PORTSEL[1–0] = 11 and additionally set
ENPLSIO = 1. This sequence is required to avoid
contention on the clock, data and/or carrier indica-
tion signals.
Write the PHY Configuration Control (PHYCC) reg-
ister to configure any non-default mode if the
10BASE-T interface is used.
Program the Logical Address Filter (LADRF) regis-
ter or the Physical Address Register (PADR). The
Internal Address Configuration (IAC) register must
be accessed first. Set the Address Change
(ADDRCHG) bit to request access to the internal
address RAM. Poll the bit until it is cleared by the
MACE device indicating that access to the internal
address RAM is permitted. In the case of an
address RAM access after hardware or software
reset (ENRCV has not been set), the MACE device
will return ADDRCHG = 0 right away. Set the
LOGADDR bit in the IAC register to select writing to
the Logical Address Filter register. Set the PHY-
ADDR bit in the IAC register to select writing to the
Physical Address Register. Either bit can be set to-
gether with writing the ADDRCHG bit. Initializing the
Logical Address Filter register requires 8 write
cycles. Initializing the Physical Address Register
requires 6 write cycles.
Write the User Test Register (UTR) to set the MACE
device into any of the user diagnostic modes such
as loopback.
Write the MAC Configuration Control (MACCC) reg-
ister as the last step in the initialization sequence to
enable the receiver and transmitter. Note that the
system must guarantee a delay of 1 ms after
power-up before enabling the receiver and transmit-
ter to allow the MACE phase lock loop to stabilize.
The Transmit Frame Control (XMTFC) and the
Receive Frame Control (RCVFC) registers can be
programmed on a per packet basis.