AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 78
AM79C940JC/W
Manufacturer Part Number
AM79C940JC/W
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C940JCW.pdf
(144 pages)
- Current page: 78 of 144
- Download datasheet (2Mb)
Programmer’s Register Model (continued)
78
Addr
12
13
14
Mnemonic
FIFOCC
MACCC
PLSCC
FIFO Configuration Control
C0
30
08
04
02
01
Media Access Control (MAC) Configuration Control
80
40
20
10
08
04
02
01
Physical Layer Signalling (PLS) Configuration Control
08
06
01
DRCVPA
DRCVBC
ENXMT
ENRCV
XMTSEL
PORTSEL [1:0]–Port Select (2 bits)
ENPLSIO
XMBRST
RCVBRST
PROM
DXMT2PD
EMBA
–
XMTFW
XMTFWU
RCVFWU
00
01
10
11
RCVFW
00
01
10
11
00
01
10
11
GPSI selected
AUI selected
10BASE-T selected
DAI port selected
Transmit Mode Select: 1
Enable Status
Disable Receive Physical Address
Enable Modified Back-off Algorithm
Disable Receive Broadcast
XX
XX
Enable Transmit
Enable Receive
Transmit FIFO Watermark (2 bits)
Transmit FIFO Watermark Update–loads XMTFW bits
Receive FIFO Watermark Update–loads
Promiscuous mode
Assert TDTREQ after 8 write cycles can be made
Assert TDTREQ after 16 write cycles can be made
Assert TDTREQ after 32 write cycles can be made
Assert RDTREQ after 16 bytes are present
Assert RDTREQ after 32 bytes are present
Assert RDTREQ after 64 bytes are present
RCVFW bits
Select Transmit Burst mode
Disable Transmit Two Part Deferral
Receive FIFO Watermark (2 bits)
Select Receive Burst mode
Contents
DO
during IDLE
R/W
R/W
R/W
R/W
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