AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 28

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

of the bits in the MAC configuration Control Register of
the internal analog circuits by 1 ns to allow for
stabilization.
If the AWAKE bit is set prior to the activation of SLEEP,
the 10BASE–T receiver and the LNKST output pin
remain operational.
If the RWAKE bit is set prior to SLEEP being asserted,
the Manchester encoder/decoder, AUI and 10BASE-T
cells remain operational, as do the SRD, SRDCLK and
SF/BD outputs.
The input on XTAL1 must remain active for the AWAKE
or RWAKE features to operate. After exit from the Auto
Wake or Remote Wake modes, activation of hardware
RESET is not required when SLEEP is reasserted.
On deassertion of SLEEP, the MACE device will go
through an internally generated hardware reset
sequence, requiring re-initialization of MACE registers.
Power Supply
DV
Digital Power
There are four Digital V
DV
Digital Ground
There are six Digital V
AV
Analog Power
There are four analog VDD pins. Special attention
should be paid to the printed circuit board layout to
avoid excessive noise on the supply to the PLL in the
Manchester encoder/decoder (pins 66 and 83 in PLCC,
pins 67 and 88 in PQFP). These supply lines should be
kept separate from the DV
power supply as is practically possible.
AV
Analog Ground
There are two analog VSS pins. Special attention
should be paid to the printed circuit board layout to
avoid excessive noise on the PLL supply in Manches-
ter encoder/decoder (pin 73 in PLCC, pin 74 in PQFP).
These supply lines should be kept separate from the
DV
practically possible.
PIN FUNCTIONS NOT AVAILABLE WITH
THE 80-PIN TQFP PACKAGE
In the 84-pin PLCC configuration, ALL the pins are
used while in the 100-pin PQFP version, 16 pins are
specified as No Connects. Moving to the 80-pin TQFP
configuration requires the removal of 4 pins. Since
Ethernet controllers with integrated 10BASE-T have
analog portions which are very sensitive to noise,
28
SS
DD
SS
DD
SS
lines as far back to the power supply as is
SS
DD
pins.
pins.
DD
lines as far back to the
Am79C940
power and ground pins are not deleted. The MACE
device does have several sets of media interfaces
which typically go unused in most designs, however.
Pins from some of these interfaces are deleted instead.
Removed are the following:
Note that pins from four separate interfaces are
removed rather than removing all the pins from a single
interface. Each of these pins comes from one of the
four sides of the device. This is done to maintain sym-
metry, thus avoiding bond out problems.
In general, the most critical of the four removed pins
are TXDAT– and SRD. Depending on the application,
either the DAI or the EADI interface may be important.
In most designs, however, this will not be the case.
PINS REMOVED FOR TQFP PACKAGE
AND THEIR EFFECTS
TXDAT–
The removal of TXDAT– means that the DAI interface is
no longer usable. The DAI interface was designed to be
used with media types that do not require DC isolation
between the MAU and the DTE. Media which do not re-
quire DC isolation can be implemented more simply
using the DAI interface, rather than the AUI interface. In
most designs this is not a problem because most media
requires DC isolation (10BASE-T, 10BASE2, 10BASE5)
and will use the AUI port. About the only media which
does not require DC isolation is 10BASE-F.
SRD
The SRD pin is an output pin used by the MACE device
to transfer a receive data stream to external address
detection logic. It is part of the EADI interface. This pin
is used to help interface the MACE device to an exter-
nal CAM device. Use of an external CAM is typically
required when an application will operate in promiscu-
ous mode and will need perfect filtering (i.e., the inter-
nal hash filter will not suffice). Example applications for
this sort of operation are bridges and routers. Lack of
perfect filtering in these applications forces the CPU to
be more involved in filtering and thus either slows the
forwarding rates achieved or forces the use of a more
powerful CPU.
DTV
The DTV pin is part of the host interface to the MACE
device. It is used to indicate that a read or write cycle
to the MACE device was successful. If DTV is not as-
serted at the end of a cycle, the data transfer was not
successful. Basically, this will happen on a write to a
full transmit FIFO or a read from an empty receive
TXDAT– (previously used for the DAI interface)
SRD (previously used for the EADI interface)
DTV (previously used for the host interface)
RXPOL (previously used as a receive frame polarity
LED driver)