AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 43

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

(MDI). Filter and transformer loss are not specified. The
10BASE-T MAU receiver squelch levels are defined to ac-
count for a 1dB insertion loss at 10 MHz, which is typical for
the type of receive filters/transformers recommended (see
the Appendix for additional details).
Normal 10BASE-T compatible receive thresholds are
employed when the LRT bit is inactive (PHY Configu-
ration Control register). When the LRT bit is set, the
Low Receive Threshold option is invoked, and the sen-
sitivity of the 10BASE-T MAU receiver is increased.
This allows longer line lengths to be employed, ex-
ceeding the 100m target distance of normal 10BASE-T
(assuming typical 24 AWG cable). The additional cable
distance attributes directly to increased signal attenua-
tion and reduced signal amplitude at the 10BASE-T
MAU receiver. However, from a system perspective,
making the receiver more sensitive means that it is also
more susceptible to extraneous noise, primarily caused
by coupling from co-resident services (crosstalk). For
this reason, it is recommended that when using the
Low Receive Threshold option that the service should
be installed on 4-pair cable only. Multi-pair cables
within the same outer sheath have lower crosstalk at-
tenuation, and may allow noise emitted from adjacent
pairs to couple into the receive pair, and be of sufficient
amplitude to falsely unsquelch the 10BASE-T
MAU receiver.
Link Test Function
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair
inactivity, Link Test pulses will be periodically sentover
the twisted pair medium to constantly monitor
medium integrity.
When the link test function is enabled, the absence of
Link Test pulses and receive data on the RXD pair will
cause the 10BASE-T MAU to go into a Link Fail state.
In the Link Fail state, data transmission, data reception,
data loopback and the collision detection functions are
disabled, and remain disabled until valid data or >5
consecutive link pulses appear on the RXD pair. Dur-
ing Link Fail, the LNKST pin is inactive (externally
pulled HIGH), and the Link Fail bit (LNKFL in the PHY
Configuration Control register) will be set. When the
link is identified as functional, the LNKST pin is driven
LOW (capable of directly driving a Link OK LED using
an integrated 12 mA driver) and the LNKFL bit will be
cleared. In order to inter-operate with systems which
do not implement link test, this function can be disabled
by setting the the Disable Link Test bit (DLNKTST in the
PHY Configuration Control register). With link test
disabled, the data driver, receiver and loopback func-
tions as well as collision detection remain enabled
irrespective of the presence or absence of data or link
pulses on the RXD pair.
Am79C940
The MACE devices integrated 10BASE-T transceiver
will mimic the performance of an externally connected
device (such as a 10BASE-T MAU connected using an
AUI). When the 10BASE-T transceiver is in link fail, the
receive data path of the transceiver must be disabled.
The MACE device will report a Loss of Carrier error
(LCAR bit in the Transmit Frame Status register) due to
the absence of the normal loopback path, for every
packet transmitted during the link fail condition. In ad-
dition, a Collision Error (CERR bit in the Transmit
Frame Status register) will also be reported (see the
section on Signal Quality Error Test Function for
additional details).
If the AWAKE bit is set in the PHY Configuration Con-
trol register prior to the assertion of the hardware
SLEEP pin, the 10BASE-T receiver remains operable,
and is able to detect and indicate (using the LNKST
output) the presence of legitimate Link Test pulses or
receive activity. The transmission of Link Test pulses is
suspended to reduce power consumption.
If the RWAKE bit is set in the PHY Configuration Con-
trol register prior to the assertion of the hardware
SLEEP pin, the 10BASE-T receiver and transmitter
functions remain active, the LNKST output is disabled,
and the EADI output pins are enabled. In addition the
AUI port (transmit and receive) remains active. Note
that since the MAC core will be in a sleep mode, no
transmit activity is possible, and the transmission of
Link Test pulses is also suspended to reduce
power consumption.
Polarity Detection and Reversal
The Twisted Pair receive function includes the ability to
invert the polarity of the signals appearing at the RXD
pair if the polarity of the received signal is reversed
(such as in the case of a wiring error). This feature al-
lows data packets received from a reverse wired RXD
input pair to be corrected in the 10BASE-T MAU prior
to transfer to the MENDEC. The polarity detection func-
tion is activated following reset or Link Fail, and will
reverse the receive polarity based on both the polarity
of any previous Link Test pulses and the polarity of
subsequent packets with a valid End Transmit
Delimiter (ETD).
When in the Link Fail state, the internal 10BASE-T
receiver will recognize Link Test pulses of either posi-
tive or negative polarity. Exit from the Link Fail state is
made due to the reception of five to six consecutive
Link Test pulses of identical polarity. On entry to the
Link Pass state, the polarity of the last five Link Test
pulses is used to determine the initial receive polarity
configuration and the receiver is reconfigured to subse-
quently recognize only Link Test pulses of the previ-
ously recognized polarity. This link pulse algorithm is
employed only until ETD polarity determination is made
as described later inthis section.
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