AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 56

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

read. The Receive Frame Status is a single location
which must be read four times to allow the four bytes of
status information associated with each frame to be
read. Further data read operations from the Receive
FIFO using the Register Address mode, will be ignored
by the MACE device (indicated by the MACE chip not
returning DTV) until all four bytes of the Receive Frame
Status have been read. Alternatively, the FIFO Direct
access mode may be used to read the Receive Frame
Status through the Receive FIFO. In either case, the
4-byte total must be read before additional receive data
can be read from the Receive FIFO. However, the
RDTREQ indication will continue to reflect the state of
the Receive FIFO as normal, regardless of whether the
Receive Frame Status has been read. DTV will not be
returned when a read operation is performed on the
Receive Frame Status location and no valid status is
present or ready.
Note that the Receive Frame Status can be read using
either the Register Address or FIFO Direct modes. For
additional details, see the section Receive FIFO Read.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to
abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the MACE device are basically colli-
sions within the slot time and automatic runt packet
deletion. The MACE device will ensure that any receive
packet which experiences a collision within 512 bit
times from the start of reception (excluding preamble)
will be automatically deleted from the Receive FIFO
with no host intervention (the state of the RPA bit in the
User Test Register; or the RCVFW bits in the FIFO
Configuration Control register have no effect on this).
This criteria will be met, regardless of whether the
receive frame was the first (or only) frame in the
Receive FIFO, or if the receive frame was queued
behind a previously received message.
Abnormal network conditions include:
These should not occur on a correctly configured 802.3
network, but may be reported if the network has been
incorrectly configured or a fault condition exists.
Host related receive exception conditions include:
(a)
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FCS errors
Framing errors
Dribbling bits
Late collision
Underflow caused by excessive reads from the
Receive FIFO (DTV will not be issued if the
Receive FIFO is empty)
Am79C940
(b)
(c)
(a) Successive read operations from the Receive FIFO
after the final byte of data/status has been read, will
cause the DTV pin to remain de-asserted during the
read operation, indicating that no valid data is present.
There will be no adverse effect on the Receive FIFO.
(b) Data present in the Receive FIFO from packets
which completed before the overflow condition
occurred, can be read out by accessing the Receive
FIFO normally. Once this data (and the associated
Receive Frame Status) has been read, the EOF indica-
tion will be asserted by the MACE device during the
first read operation takes place from the Receive FIFO,
for the packet which suffered the overflow. If there were
no other packets in the FIFO when the overflow
occurred, the EOF will be asserted on the first read
from the FIFO. In either case, the EOF indication will be
accompanied by assertion of the INTR pin, providing
that the RCVINTM bit in the Interrupt Mask Register is
not set. If the Register Address mode is being used, the
host is required to access the Receive Frame Status
location using four separate read cycles. Further
access to the Receive FIFO will be ignored by the
MACE device until all four bytes of the Receive Frame
Status have been read. DTV will not be returned if a
Receive FIFO read is attempted. If the FIFO Direct
mode is being used, the host can read the Receive
Frame Status through the Receive FIFO, but the host
must be aware that the subsequent four cycles will
yield the receive status bytes, and not data from the
same or a new packet. Only the OFLO bit will be valid
in the Receive Frame Status, other error/status and the
RCVCNT fields are invalid.
While the Receive FIFO is in the overflow condition, it
is deaf to additional receive data on the network. How-
ever, the MACE device internal address detect logic
continues to operate and counts the number of packets
that would have been passed to the host under normal
(non overflow) conditions. The Missed Packet Count
(MPC) is an 8-bit count (in register 24) that maintains
the number of packets which pass the address match
criteria, and complete without collision. The MPC
counter will wrap around when the maximum count of
255 is reached, setting the MPCO (Missed Packet
Count Overflow) bit in the Interrupt Register, and
asserting the INTR pin providing that MPCOM (Missed
Packet Count Overflow Mask) in the Interrupt Mask
Register is clear. MPCO will be cleared (the interrupt
will be unmasked) after hardware or software reset.
However, until the first time that the receiver is enabled,
MPC will not increment, hence no interrupt will occur
due to missed packets after a reset.
Overflow caused by lack of host reads from the
Receive FIFO
Missed packets due to lack of host reads from
the Receive FIFO and/or the Receive Frame
Status