AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 67

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RES
DRCVPA
DRCVBC
ENXMT
ENRCV
modified
EMBA is cleared by activation of
the RESET pin or SWRST bit.
Reserved. Read as zeroes.
Always write as zeroes.
Disable
Address. When set, the physical
address detection (Station or
node ID) of the MACE device will
be disabled. Packets addressed
to the nodes individual physical
address will not be recognized
(although the packet may be
accepted by the EADI mecha-
nism). DRCVPA is cleared by
activation of the RESET pin or
SWRST bit.
Disable
When set, disables the MACE
device
broadcast messages. Used for
protocols that do not support
broadcast addressing, except as
a function of multicast. DRCVBC
is cleared by activation of the
RESET pin or SWRST bit
(broadcast messages will be
received).
Enable
ENXMT = 1 enables transmis-
sion. With ENXMT = 0, no trans-
mission will occur. If ENXMT is
written as 0 during frame trans-
mission, a packet transmission
which is incomplete will have a
guaranteed
appended before the internal
Transmit FIFO is cleared. No
subsequent attempts to load the
FIFO should be made until
ENXMT is set and TDTREQ is
asserted. ENXMT is cleared by
activation of the RESET pin or
SWRST bit.
Enable Receive. Setting ENRCV
= 1 enables reception of frames.
With ENRCV = 0, no frames will
be received from the network
into the internal FIFO. When
ENRCV is written as 0, any
receive
progress will be completed (and
valid data contained in the
RCVFIFO can be read by the
host) and the MACE device will
enter the monitoring state for
missed
clearing the ENRCV bit disables
the assertion of RDTREQ. If
ENRCV is cleared during re-
from
packets.
frame
Receive
Transmit.
Receive
backoff
CRC
responding
currently
Note
Broadcast.
algorithm.
Physical
violation
Setting
that
Am79C940
to
in
PLS Configuration
Control (PLSCC)
All bits within the PLS Configuration Control register
are cleared upon a hardware or software reset. Bit
assignments are as follows:
Bit
Bit 7-4
Bit 3
Bit 2-1
RES
RES
RES
XMTSEL
PORTSEL
[1-0]
Name
RES
RES
ceive
cleared for a long time and if the
tail end of the receive frame cur-
rently in progress is longer than
the amount of space available in
the Receive FIFO, Receive
FIFO overflow will occur. How-
ever, even with RDTREQ deas-
serted, if there is valid data in the
Receive FIFO to be read, suc-
cessful slave reads to the
Receive FIFO can be executed
(indicated by valid DTV). It is the
host’s responsibility to avoid the
overflow situation. ENRCV is
cleared by activation of the
RESET pin or SWRST bit.
Description
Reserved. Read as zeroes.
Always write as zeroes.
Transmit Mode Select. XMTSEL
provides control over the AUI
DO+ and DO– operation while
the MACE device is not transmit-
ting. With XMTSEL = 0, DO+
and DO will be equal during
transmit idle state, providing
zero differential to operate trans-
former coupled loads. The turn
off and return to zero delays are
controlled
XMTSEL = 1, DO+ is positive
with respect to DO during the
transmit idle state .
Port Select. PORTSEL is used
to select between the AUI,
10BASE–T, DAI or GPSI ports
of the MACE device. PORTSEL
is cleared by hardware or soft-
ware reset. PORTSEL will deter-
mine which of the interfaces is
used during normal operation, or
tested when utilizing the loop-
back options (LOOP [1-0]) in the
User Test Register. Note that
the PORTSEL [1–0] program-
ming will be overridden if the
ASEL bit in the PHY Configura-
tion Control register is set.
XMTSEL
activity
PORTSEL [1-0]
internally.
(REG ADDR 14)
and
ENPLSIO
remains
With
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