AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 23

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

10BASE-T INTERFACE
TXD+, TXD–
Transmit Data (Output)
10BASE–T port differential drivers.
TXP+, TXP–
Transmit Pre-Distortion (Output)
Transmit wave form differential driver for pre-distortion.
RXD+, RXD–
Receive Data (Input)
10BASE–T port differential receiver. These pins should
be externally terminated to reduce power consumption
if the 10BASE–T interface is not used.
LNKST
Link Status (OutputOpen Drain)
This pin is driven LOW if the link is identified as func-
tional. If the link is determined to be nonfunctional, due
to missing idle link pulses or data packets, then this pin
is not driven (requires external pull-up). In the LOW
output state, the pin is capable of sinking a maximum
of 12 mA and can be used to drive an LED.
This feature can be disabled by setting the Disable Link
Test (DLNKTST) bit in the PHY Configuration Control
register. In this case the internal Link Test Receive
function is disabled, the LNKST pin will be driven LOW,
and the Transmit and Receive functions will remain
active regardless of arriving idle link pulses and data.
The internal 10BASE-T MAU will continue to generate
idle link pulses irrespective of the status of the
DLNKTST bit.
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
SLEEP
0
1
1
1
1
1
PORTSEL
[1-0]
XX
XX
00
01
10
11
ENDPLSIO
STDCLK Configuration
X
1
1
1
1
0
Am79C940
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
Interface Description
RXPOL
Receive Polarity (Output, Open Drain)
The twisted pair receiver is capable of detecting a
receive signal with reversed polarity (wiring error). The
RXPOL pin is normally in the LOW state, indicating
correct polarity of the received signal. If the receiver
detects a received packet with reversed polarity, then
this pin is not driven (requires external pull-up) and the
polarity of subsequent packets are inverted. In the
LOW output state, this pin is capable of sinking a
maximum of 12mA and can be used to drive an LED.
The polarity correction feature can be disabled by
setting the Disable Auto Polarity Correction (DAPC) bit
in the PHY Configuration Control register. In this case,
the Receive Polarity correction circuit is disabled and
the internal receive signal remains non-inverted,
irrespective of the received signal. Note that RXPOL
will continue to reflect the polarity detected by the
receiver.
General Purpose Serial Interface (GPSI)
STDCLK
Serial Transmit Data Clock (Input/Output)
When either the AUI, 10BASE–T or DAI port is
selected, STDCLK is an output operating at one half the
crystal or XTAL1 frequency. STDCLK is the encoding
clock for Manchester data transferred to the output of
either the AUI DO pair, the 10BASE-T TXD /TXP
pairs, or the DAI port TXDAT pair. When using the
GPSI port, STDCLK is an input at the network data rate,
provided by the external Manchester encode/decoder,
to strobe out the NRZ data presented on the TXDAT+
output. This is also required for internal loopbacks while
in GPSI mode.
High Impedance
STDCLK Output
STDCLK Output
STDCLK Output
STDCLK Output
High Impedance (Note 2)
Pin Function
23