AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 62

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 3–0 XMTFC
Interrupt Register (IR)
All status bits are set upon occurrence of an event and
cleared when read. The resister is read only. In addition
all status bits are cleared by hardware or software
reset. Bit assignments for the register are as follows:
Bit
Bit 7
Bit 6
62
JAB BABL CERR RDVCCO
[3–0]
JAB
BABL
Name
15, additional receive frames will
be ignored, and the Missed
Packet Count (MPC) register will
be incremented for frames which
match the internal address(es)
of the MACE device.
Transmit Frame Count. The
(read only) count of the frames in
the Transmit FIFO. A frame is
counted when the last byte is put
in the FIFO. The counter is dec-
remented when XMTSV (in the
Transmit Frame Status and Poll
Register) is set and the Transmit
Frame Status read access is
performed.
Description
Jabber Error. JAB indicates that
the MACE device attempted to
transmit for an excessive time
period (20–150 ms), when using
either the DAI port or the
10BASE–T port. If the internal
jabber
transmission, the transmit bit
stream will be interrupted, until
the internal transmission ceases
and the unjab timer (0.5 s 0.25
s) expires. The jabber function
will be disabled, and JAB will not
be set, regardless of transmis-
sion length, when either the AUI
or
selected.
JAB is READ/CLEAR only, and
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by acti-
vation of the RESET pin or
SWRST bit.
Babble Error. BABL is the
transmitter time-out error. It in-
dicates that the transmitter has
been on the channel longer
than the time required to send
the maximum packet. It will be
set after 1519 bytes (or great-
er) have been transmitted. The
MACE device will continue to
transmit until the current pack-
et transmission is over. The
INTR pin will be activated if the
RNTPCO MPCO RCVINT
GPSI
timer
ports
expires
(REG ADDR 8)
have
XMTINT
during
been
Am79C940
Bit 5
Bit 4
CERR
RCVCCO
corresponding
BABLM = 0.
BABL is READ/CLEAR only,
and is set by the MACE device
and reset when read. Writing
has no effect. It is also cleared
by activation of the RESET pin
or SWRST bit.
Collision Error. CERR indicates
the absence of the Signal Quali-
ty Error Test (SQE Test) mes-
sage after a packet transmis-
sion. The SQE Test message is
a transceiver test feature. Detec-
tion depends on the MACE net-
work interface selected. In all
cases, CERR will be set if the
MACE device failed to observe
the SQE Test message within 20
network bit times after the pack-
et transmission ended. When
CERR is set, the INTR pin will be
activated if the corresponding
mask bit CERRM = 0.
When the AUI port is selected,
the SQE Test message is
returned over the CI
brief (5-15 bit times) burst of 10
MHz
10BASE–T port is selected,
CERR will be reported after a
transmission only when the
internal transceiver is in the link
fail state (LNKST pin = HIGH).
When the GPSI port is selected,
the CLSN pin must be asserted
by the external encoder/decoder
to provide the SQE Test func-
tion. When the DAI port is select-
ed, CERR will not be reported at
any time.
CERR is READ/CLEAR only. It
is set by the MACE and reset
when read. Writing has no
effect. It is also cleared by
activation of the RESET pin or
SWRST bit.
Receive Collision Count Over-
flow. Indicates that the Receive
Collision Count register rolled
over at a value of 255 receive
collisions. Receive collisions are
defined as received frames
which suffered a collision. The
INTR pin will be activated if the
corresponding mask bit RCVC-
COM = 0. Note that the RCVCC
value returned in the Receive
Frame Status (RFS3) will freeze
at a value of 255, whereas this
register
activity.
based
mask
When
version
pair as a
the
bit
of