AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 66

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 2
Bit 1
66
RCVFWU
XMTBRST Transmit Burst. When set, the
Transmit FIFO Watermark bits.
The XMTFW can be written at
any point, and will be read back
as written. However, the new
value in the XMTFW bits will be
ignored until XMTFWU is set (or
the transmit path is reset due to
a retry failure). The recommend-
ed procedure to change the
XMTFW is to write the new value
with XMTFWU set, in a single
write
should be empty and all transmit
activity complete before attempt-
ing a watermark update, since
the XMTFIFO will be reset to
allow the new pointer values to
be loaded. It is recommended
that the transmitter be disabled
by clearing the ENXMT bit.
XMTFWU will be cleared by the
MACE device after the new
XMTFW value has been loaded,
or by activation of the RESET
pin or SWRST bit.
Receive
Update. Allows update of the
Receive FIFO Watermark bits.
The RCVFW bits can be written
at any point, and will read back
as written. However, the new
value in the RCVFW bits will be
ignored until RCVFWU is set.
The recommended procedure to
change the RCVFW is to write
the new value with RCVFWU
set, in a single write cycle. The
RCVFIFO should be empty
before attempting a watermark
update, since the RCVFIFO will
be reset to allow the new pointer
values to be loaded. It is recom-
mended that the receiver be dis-
abled by clearing the ENRCV
bit. RCVFWU will be cleared by
the MACE device after the new
RCVFW value has been loaded,
or by activation of the RESET
pin or SWRST bit.
transmit burst mode is selected.
The behavior of the Transmit
FIFO
hence
TDTREQ,
TDTREQ will be deasserted if
there are only two bytes of space
available in the XMTFIFO (so
that a full word write can still
occur) or if four bytes of space
exist and the EOF pin is assert-
ed by the host.TDTREQ will be
cycle.
high
the
FIFO
will
watermark,
de-assertion
The
be
Watermark
XMTFIFO
modified.
and
Am79C940
of
Bit 0
MAC Configuration
Control (MACCC)
This register programs the transmit and receive opera-
tion and behavior of the internal MAC engine. All bits
within the MAC Configuration Control register are
cleared upon hardware or software reset. Bit
assignments are as follows:
Bit
Bit 7
Bit 6
Bit 5
PROM
DXMT2PD EMBA RES
RCVBRST Receive Burst. When set, the
PROM
DXMT2PD Disable
EMBA
Name
asserted
normal and burst modes, when
there is sufficient space in the
XMTFIFO to allow the specified
number of write cycles to occur
(programmed by the XMTFW
bits).
Cleared by activation of the
RESET pin or SWRST bit.
receive burst mode is selected.
The behavior of the Receive
FIFO low watermark, and hence
the de-assertion of RDTREQ,
will be modified. RDTREQ will
de-assert when there are only
2-bytes of data available in the
RCVFIFO (so that a full word
read can still occur).
RDTREQ will be asserted identi-
cally in both normal and burst
modes, when a minimum of
64-bytes have been received for
a new frame (or a runt packet
has been received and RPA is
set). Once the 64-byte limit has
been exceeded, RDTREQ will
be asserted providing there is
sufficient data in the RCVFIFO
to exceed the threshold, as pro-
grammed by the RCVFW bits.
Cleared by activation of the
RESET pin or SWRST bit.
Description
Promiscuous. When PROM is
set all incoming frames are
received regardless of the desti-
nation
cleared by activation of the
RESET pin or SWRST bit.
Deferral. When set, disables the
transmit two part deferral option.
DXMT2PD
activation of the RESET pin or
SWRST bit.
Enable Modified Back-off Algo-
rithm. When set, enables the
DRCVPA
address.
Transmit
identically
DRCVBC
is
(REG ADDR 13)
ENXMT
cleared
PROM
Two
in
ENRCV
both
Part
by
is