MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 18

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
10. AC characteristics assume
11. For auto precharge mode, the precharge timing budget (
12. CLK must be toggled a minimum of two times during this period.
13. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
14. Timing is specified by
15. Timing is specified by
16. Timing is specified by
17. Based on
timing must be derated. Input setup times require an additional 50ps for each 100
mV/ns reduction in slew rate. Input hold times remain unchanged. If the slew rate ex-
ceeds 4.5V/ns, functionality is uncertain.
after the first clock delay and after the last WRITE is executed.
ing parameter.
cle rate.
t
CK (MIN), CL = 3.
Electrical Specifications – AC Operating Conditions
t
t
t
CKS. Clock(s) specified as a reference only at minimum cycle rate.
WR plus
WR.
18
t
T = 1ns. For command and address input slew rates <0.5V/ns,
t
RP. Clock(s) specified as a reference only at minimum cy-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x32 Mobile LPSDR SDRAM
t
RP) begins at
© 2010 Micron Technology, Inc. All rights reserved.
t
RP – (1 ×
t
CKns),