MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 6

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

General Description
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
The 1Gb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory con-
taining 1,073,741,824 bits. It is internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 col-
umns by 32 bits. In the reduced page size option, each of the x32’s 268,435,456-bit
banks is organized as 16,384 rows by 512 columns by 32 bits.
Mobile LPSDR offers substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-ad-
dress generation, the ability to interleave between internal banks in order to hide pre-
charge time, and the capability to randomly change column addresses on each clock cy-
cle during a burst access.
Note:
1. Throughout the data sheet, various figures and text refer to DQs as DQ. DQ should be
interpreted as any and all DQ collectively, unless specifically stated otherwise. Addition-
ally, x32 is divided into four bytes. For DQ[7:0], DQM refers to DQM0. For DQ[15:8],
DQM refers to DQM1. For DQ[23:16], DQM refers to DQM2, and for DQ[31:24], DQM
refers to DQM3.
2. Complete functionality is described throughout the document; any page or diagram
may have been simplified to convey a topic and may not be inclusive of all require-
ments.
3. Any specific requirement takes precedence over a general statement.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x32 Mobile LPSDR SDRAM
General Description
© 2010 Micron Technology, Inc. All rights reserved.