MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 34
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MT48H32M32LFB5-6 IT:B
Manufacturer Part Number
MT48H32M32LFB5-6 IT:B
Description
Manufacturer
Micron
Datasheet
1.MT48H32M32LFB5-6_ITB.pdf
(81 pages)
- Current page: 34 of 81
- Download datasheet (3Mb)
Initialization
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Low-power SDRAM devices must be powered up and initialized in a predefined man-
ner. Using initialization procedures other than those specified may result in undefined
operation. After power is simultaneously applied to V
ble (a stable clock is defined as a signal cycling within timing constraints specified for
the clock ball), the device requires a 100μs delay prior to issuing any command other
than a COMMAND INHIBIT or NOP . Starting at some point during this 100μs period
and continuing at least through the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
After the 100μs delay is satisfied by issuing at least one COMMAND INHIBIT or NOP
command, a PRECHARGE command must be issued. All banks must then be pre-
charged, which places the device in the all banks idle state.
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the device is ready for mode register programming. Be-
cause the mode register powers up in an unknown state, it should be loaded prior to
issuing any operational command.
34
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x32 Mobile LPSDR SDRAM
DD
and V
© 2010 Micron Technology, Inc. All rights reserved.
DDQ
and the clock is sta-
Initialization
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