MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 46

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Figure 17: READ-to-WRITE
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Note:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 17
(page 46) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 18 (page 47) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last de-
sired data element is valid, where x = CL - 1. This is shown in Figure 19 (page 47) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
Command
Address
1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
DQM
CLK
DQ
to any bank. If a burst of one is used, DQM is not required.
T0
Col n
READ
Bank,
T1
NOP
Transitioning data
T2
NOP
46
T3
D
NOP
OUT
t HZ
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t CK
n
Don’t Care
T4
WRITE
Col b
Bank,
1Gb: x32 Mobile LPSDR SDRAM
D
IN
b
t
DS
t
RP is met. Note that part of
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READ Operation