MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 52

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

WRITE Operation
Figure 24: WRITE Burst
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Note:
WRITE bursts are initiated with a WRITE command, as shown in Figure 8 (page 26). The
starting column and bank addresses are provided with the WRITE command and auto
precharge is either enabled or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst. For the generic WRITE
commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 24 (page 52)). A continuous page burst continues until terminated;
at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previ-
ous WRITE command, and the data provided coincident with the new command ap-
plies to the new command (see Figure 25 (page 53)). Data n + 1 is either the last of a
burst of two or the last desired data element of a longer burst.
Mobile LPSDR devices use a pipelined architecture and therefore do not require the 2n
rule associated with a prefetch architecture. A WRITE command can be initiated on any
clock cycle following a previous WRITE command. Full-speed random write accesses
within a page can be performed to the same bank, as shown in Figure 26 (page 54), or
each subsequent WRITE can be performed to a different bank.
Command
Address
1. BL = 2. DQM is LOW.
CLK
DQ
WRITE
Bank,
Col n
T0
D
n
IN
Transitioning data
NOP
n + 1
T1
D
IN
52
NOP
T2
Don’t Care
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
NOP
1Gb: x32 Mobile LPSDR SDRAM
© 2010 Micron Technology, Inc. All rights reserved.
WRITE Operation