MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 41

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Partial-Array Self Refresh
Output Drive Strength
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
(TCSR) bits has no effect on the device. The self refresh oscillator will continue refresh
at the optimal factory-programmed rate for the device temperature.
For further power savings during self refresh, the partial-array self refresh (PASR) feature
enables the controller to select the amount of memory to be refreshed during self re-
fresh. The refresh options are:
• Full array: banks 0, 1, 2, and 3
• One-half array: banks 0 and 1
• One-quarter array: bank 0
• One-eighth array: bank 0 with row address most significant bit (MSB) = 0
• One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
READ and WRITE commands can still be issued to any bank selected during standard
operation, but only the selected banks or segments of a bank in PASR are refreshed dur-
ing self refresh. It is important to note that data in unused banks or portions of banks is
lost when PASR is used.
Because the device is designed for use in smaller systems that are typically point-to-
point connections, an option to control the drive strength of the output buffers is provi-
ded. Drive strength should be selected based on the expected loading of the memory
bus. There are four supported settings for the output drivers: 25Ω, 37Ω, 55Ω, and 80Ω
internal impedance. These are full, three-quarter, one-half, and one-quarter drive
strengths, respectively.
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1Gb: x32 Mobile LPSDR SDRAM
Extended Mode Register
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