MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 36

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Mode Register
Figure 11: Mode Register Definition
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Mn+2 Mn+1
0
0
1
1
0
1
0
1
Mn+2
n+2 n+1
0
Mode Register Definition
Base mode register
Reserved
Extended mode register
Reserved
BA1
M9
0
1
Mn+1
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and
Mn + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must wait
t
will result in unspecified operation.
0
Programmed burst length
Single location access
BA0
MRD before initiating the subsequent operation. Violating either of these requirements
M8
0
–
Write Burst Mode
An
Mn
n
Reserved*
M7
0
–
...
...
...
Normal operation
All other states reserved
Operating Mode
10
A10
M10
WB
M6
0
0
0
0
1
1
1
1
A9
M9
9
Op mode
M5
0
0
1
1
0
0
1
1
M8
A8
8
M4
0
1
0
1
0
1
0
1
A7
M7
7
CAS Latency
CAS latency
36
M6
A6
6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
5
A5
M5
M4
4
A4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
BT
M3
A3
3
M2
Burst length
1Gb: x32 Mobile LPSDR SDRAM
0
0
0
0
1
1
1
1
A2
M2
2
M1
*Should be programmed to 0
0
0
1
1
0
0
1
1
to ensure compatibility
with future devices.
M1
1
A1
M3
M0
0
1
0
1
0
1
0
1
0
1
M0
A0
0
Continuous
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
1
2
4
8
Address bus
Mode
register (Mx)
Burst Length
© 2010 Micron Technology, Inc. All rights reserved.
Reserved
Reserved
Reserved
Reserved
Mode Register
M3 = 1
1
2
4
8