MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 59

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Figure 32: WRITE – DQM Operation
Burst Read/Single Write
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Command
BA0, BA1
Address
DQM
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Bank
T0
Row
Row
t CKH
t CMH
t AH
t AH
t AH
Note:
t RCD
t CK
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
T1
NOP
1. For this example, BL = 4.
Disable auto precharge
Enable auto precharge
t CMS
t CL
t DS
Column m
WRITE
D
T2
Bank
IN
t CMH
t DH
m
t CH
T3
NOP
59
t DS
D
IN
T4
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
m + 2
t DH
1Gb: x32 Mobile LPSDR SDRAM
t DS
D
IN
T5
NOP
m + 3
t DH
© 2010 Micron Technology, Inc. All rights reserved.
NOP
T6
WRITE Operation
NOP
T7
Don’t Care