MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 61

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Figure 33: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after
istered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 40 (page 67)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
t
WR is met, where
T2
CL = 3 (bank n)
NOP
61
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
T4
WR begins when the WRITE to bank m is reg-
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
a
1Gb: x32 Mobile LPSDR SDRAM
T5
NOP
D
a + 1
OUT
PRECHARGE Operation
T6
NOP
D
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OUT
d
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
d + 1
OUT