MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 9

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Table 3: VFBGA Ball Descriptions
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
CAS#, RAS#,
DQM[3:0]
BA0, BA1
DQ[31:0]
Symbol
(90-ball)
A[13:0]
V
WE#
DNU
V
CKE
CLK
V
CS#
V
NC
DDQ
SSQ
DD
SS
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Type
I/O
–
–
Note:
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output regis-
ters.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), deep power-down (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
coder. All commands are masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-
tered.
Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are High-Z (two-clock latency) during a READ cycle. For the x32, DQM0 corre-
sponds to DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds to DQ[23:16], and
DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as
DQM.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied. BA0 and BA1 become “Don’t Care” when registering an
ALL BANK PRECHARGE (A10 HIGH).
Address inputs: Addresses are sampled during the ACTIVE command (row) and READ/WRITE
command [column); with A10 defining auto precharge] to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to de-
termine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The ad-
dress inputs also provide the op-code during a LOAD MODE REGISTER command. The maxi-
mum address range is dependent upon configuration. Unused address pins become RFU.
Data input/output: Data bus.
DQ power: Provide isolated power to DQ for improved noise immunity.
DQ ground: Provide isolated ground to DQ for improved noise immunity.
Core power supply.
Ground.
Do not use: Must be grounded or left floating.
Internally not connected. These balls can be left unconnected but it is recommended that
they be connected to V
1. Balls marked RFU may or may not be connected internally. These balls should not be
used. Contact the factory for details.
SS
.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
1Gb: x32 Mobile LPSDR SDRAM
© 2010 Micron Technology, Inc. All rights reserved.
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