MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 76

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Power-Down
Figure 47: Power-Down Mode
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Command
BA0, BA1
Address
Precharge all
active banks
DQM
CKE
CLK
A10
DQ
High-Z
t CMS
t CKS
PRECHARGE
t AS
Single bank
All banks
Bank(s)
T0
t CMH
t CKH
t AH
Note:
Two clock cycles
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting
All banks idle, enter
power-down mode
t CK
1. Violating refresh requirements during power-down may result in a loss of data.
T1
NOP
t CL
t CKS
T2
NOP
t CH
Input buffers gated off
while in power-down mode
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Exit power-down mode
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CKS).
1Gb: x32 Mobile LPSDR SDRAM
t CKS
Tn + 1
NOP
All banks idle
© 2010 Micron Technology, Inc. All rights reserved.
Tn + 2
Power-Down
ACTIVE
Row
Bank
Row
Don’t Care