C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 109

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

18.2. Security Options
The C8051T620/621/320/321/322/323 devices provide security options to prevent unauthorized viewing of
proprietary program code and constants. A security byte stored at location 0x3FF8 in the EPROM address
space can be used to lock the program memory from being read or written across the C2 interface. The
lock byte can always be read regardless of the security settings. Table 18.1 shows the security byte decod-
ing. Refer to “Figure 15.2. Program Memory Map” on page 86 for the location of the security byte in
EPROM memory.
Important Note: Once the security byte has been written, there are no means of unlocking the device.
Locking memory from write access should be performed only after all other code has been successfully
programmed to memory.
18.3. EPROM Writing Guidelines
Any system which contains routines which write EPROM memory from software involves some risk that
the write routines will execute unintentionally if the CPU is operating outside its specified operating range
of V
result in alteration of EPROM memory contents causing a system failure.
The following guidelines are recommended for any system which contains routines which write EPROM
memory from code.
18.3.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. Make certain that the minimum V
3. Enable the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
this rise time specification, then add an external V
holds the device in reset until V
possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based
systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
Monitor reset source must be enabled to write the EPROM without generating an EPROM Error Device
Reset.
source inside the functions that write EPROM memory. The V
placed just after the instruction to set PSWE to a 1, but before the EPROM write operation instruction.
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example,"RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
are initialization code which enables other reset sources, such as the Missing Clock Detector, for
DD
DD
, system clock frequency, or temperature. This accidental execution of EPROM modifying code can
monitor and enabling the V
Bits
7–4
3–0
DD
monitor and enable the V
Write Lock: Clearing any of these bits to logic 0 prevents all code
memory from being written across the C2 interface.
Read Lock: Clearing any of these bits to logic 0 prevents all code
memory from being read across the C2 interface.
Table 18.1. Security Byte Decoding
DD
DD
DD
reaches V
monitor as a reset source. Note: Both the VDD Monitor and the VDD
C8051T620/621/320/321/322/323
rise time specification of 1 ms is met. If the system cannot meet
RST
Rev. 1.1
DD
and re-asserts RST if V
DD
DD
monitor and enable the V
monitor as a reset source as early in code as
brownout circuit to the RST pin of the device that
Description
DD
monitor enable instructions should be
DD
DD
drops below V
monitor as a reset
RST
.
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