C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 110

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
18.3.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set to a 1. There should be
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been
10.Make certain that the EPROM write pointer variables are not located in XRAM. See your compiler
11. Add address bounds checking to the routines that write EPROM memory to ensure that a routine called
18.3.3. System Clock
12.If operating from an external crystal, be advised that crystal performance is susceptible to electrical
13.If operating from the external oscillator, switch to the internal oscillator during EPROM write operations.
18.4. Program Memory CRC
A CRC engine is included on-chip which provides a means of verifying EPROM contents once the device
has been programmed. The CRC engine is available for EPROM verification even if the device is fully read
and write locked, allowing for verification of code contents at any time.
The CRC engine is operated through the C2 debug and programming interface, and performs 16-bit CRCs
on individual 256-Byte blocks of program memory, or a 32-bit CRC on the entire memory space. To prevent
hacking and extrapolation of security-locked source code, the CRC engine will only allow CRCs to be per-
formed on contiguous 256-Byte blocks beginning on 256-Byte boundaries (lowest 8-bits of address are
0x00). For example, the CRC engine can perform a CRC for locations 0x0400 through 0x04FF, but it can-
not perform a CRC for locations 0x0401 through 0x0500, or on block sizes smaller or larger than 256
Bytes.
18.4.1. Performing 32-bit CRCs on Full EPROM Content
A 32-bit CRC on the entire EPROM space is initiated by writing to the CRC1 byte over the C2 interface.
The CRC calculation begins at address 0x0000, and ends at the end of user EPROM space. The EPBusy
bit in register C2ADD will be set during the CRC operation, and cleared once the operation is complete.
The 32-bit results will be available in the CRC3-0 registers. CRC3 is the MSB, and CRC0 is the LSB. The
polynomial used for the 32-bit CRC calculation is 0x04C11DB7. Note: If a 16-bit CRC has been performed
since the last device reset, a device reset should be initiated before performing a 32-bit CRC operation.
18.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks
A 16-bit CRC of individual 256-byte blocks of EPROM can be initiated by writing to the CRC0 byte over the
C2 interface. The value written to CRC0 is the high byte of the beginning address for the CRC. For exam-
ple, if CRC0 is written to 0x02, the CRC will be performed on the 256-bytes beginning at address 0x0200,
and ending at address 0x2FF. The EPBusy bit in register C2ADD will be set during the CRC operation, and
cleared once the operation is complete. The 16-bit results will be available in the CRC1-0 registers. CRC1
is the MSB, and CRC0 is the LSB. The polynomial for the 16-bit CRC calculation is 0x1021.
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example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly
verify this.
exactly one routine in code that sets PSWE to a 1 to write EPROM bytes.
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area.
reset to '0'. Any interrupts posted during the EPROM write operation will be serviced in priority order
after the EPROM operation has been completed and interrupts have been re-enabled by software.
documentation for instructions regarding how to explicitly locate variables in different memory areas.
with an illegal address does not result in modification of the EPROM.
interference and is sensitive to layout and to changes in temperature. If the system is operating in an
electrically noisy environment, use the internal oscillator or an external CMOS clock.
The external oscillator can continue to run, and the CPU can switch back to the external oscillator after
the EPROM operation has completed.
Rev. 1.1