C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 114

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up the system. Refer to Section “20.6. PCA Watchdog Timer
Reset” on page 120 for more information on the use and configuration of the WDT.
19.2. Stop Mode
Setting the stop mode Select bit (PCON.1) causes the controller core to enter stop mode as soon as the
instruction that sets the bit completes execution. In stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering stop mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout.
By default, when in stop mode the internal regulator is still active. However, the regulator can be config-
ured to shut down while in stop mode to save power. To shut down the regulator in stop mode, the
STOPCF bit in register REG01CN should be set to 1 prior to setting the STOP bit (see SFR Definition
11.1). If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capa-
ble of resetting the device.
19.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the high-frequency internal oscillator
and go into suspend mode as soon as the instruction that sets the bit completes execution. All internal reg-
isters and memory maintain their original data. The CPU is not halted in Suspend, so code can still be exe-
cuted using an oscillator other than the internal High Frequency Oscillator. Most digital peripherals are not
active in suspend mode. The exception to this are the USB0 Transceiver, Port Match feature, and Timer 3,
when it is run from an external oscillator source or the internal low-frequency oscillator.
Suspend mode can be terminated by four types of events: a port match (described in Section “22.5. Port
Match” on page 144), a Timer 3 overflow (described in Section “28.3. Timer 3” on page 256), resume sig-
nalling on the USB data pins, or a device reset event. Note that in order to run Timer 3 in suspend mode,
the timer must be configured to clock from either the external clock source or the internal low-frequency
oscillator source. When suspend mode is terminated, the device will continue execution on the instruction
following the one that set the SUSPEND bit. If the wake event (USB0 resume signalling, port match, or
Timer 3 overflow) was configured to generate an interrupt, the interrupt will be serviced upon waking the
device. If suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal reset
sequence and begins program execution at address 0x0000.
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