C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 274

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
Note that the 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 29.5, where PCA0L is the value of the PCA0L register
at the time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.
29.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:






The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 29.5, this results in a WDT
274
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2 – CPS0 bits).
Load PCA0CPL4 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH4.
PCA0CPL4
C
D
L
I
W
D
E
T
PCA0MD
W
D
C
K
L
PCA0CPH4
C
P
S
2
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled
Write to
C
P
S
1
C
P
S
0
Equation 29.5. Watchdog Timer Offset in PCA Clocks
C
E
F
Offset
8-bit Adder
=

Enable
Adder
256 PCA0CPL4

Enable
Rev. 1.1
PCA0CPH4
Comparator
PCA0H
8-bit

+

256 PCA0L
Match
–
PCA0L Overflow

Reset