C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 120

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
20.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “29.4. Watchdog Timer Mode” on
page 273; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
20.7. EPROM Error Reset
If an EPROM program read or write targets an illegal address, a system reset is generated. This may occur
due to any of the following:



The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaf-
fected by this reset.
20.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
20.9. USB Reset
Writing 1 to the USBRSF bit in register RSTSRC selects USB0 as a reset source. With USB0 selected as
a reset source, a system reset will be generated when either of the following occur:
1. RESET signaling is detected on the USB network. The USB Function Controller (USB0) must be
2. A falling or rising voltage on the VBUS pin matches the edge polarity selected by the VBPOL bit in
The USBRSF bit will read 1 following a USB reset. The state of the /RST pin is unaffected by this reset.
120
Programming hardware attempts to write or read an EPROM location which is above the user code
space address limit.
An EPROM read from firmware is attempted above user code space. This occurs when a MOVC
operation is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
enabled for RESET signaling to be detected. See Section “23. Universal Serial Bus Controller (USB0)”
on page 155 for information on the USB Function Controller.
register REG01CN. See Section “11. Voltage Regulators (REG0 and REG1)” on page 59 for details on
the VBUS detection circuit.
Rev. 1.1