C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 137

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

22.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When
a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (exclud-
ing UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when
assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in
the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Because of the nature of the Priority Crossbar Decoder, not all peripherals can be located on all port pins.
Figure 22.3 shows the possible pins on which peripheral I/O can appear.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. The Crossbar skips selected pins as if they were
already assigned, and moves to the next unassigned pin.
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when a UART is selected, the Crossbar assigns both pins associated with the UART (TX
and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to
P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned. Figure 22.4 and Figure 22.5 show examples of how the crossbar assigns
peripherals according to the XBRn and PnSKIP register settings.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
Digital Function
External Interrupt 0
External Interrupt 1
Port Match
Table 22.3. Port I/O Assignment for External Digital Event Capture Functions
C8051T620/621/320/321/322/323
Potentially Assignable Port Pins
Rev. 1.1
P0.0 - P0.7
P0.0 - P0.7
P0.0 - P1.7
P0MASK, P0MAT
P1MASK, P1MAT
SFR(s) used for
Assignment
IT01CF
IT01CF
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