C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 178

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
USB Register Definition 23.17. E0CSR: USB0 Endpoint0 Control
USB Register Address = 0x11
178
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
DATAEND Data End Bit.
SSUEND Serviced Setup End
SOPRDY Serviced OPRDY Bit. Software should write 1 to this bit
INPRDY
OPRDY
SUEND
SDSTL
STSTL
Name
SSUEND
R/W
7
0
Bit.
Send Stall Bit.
Software can write 1 to this bit to terminate the current transfer (due to an error condi-
tion, unexpected transfer request, etc.). Hardware will clear this bit to 0 when the STALL
handshake is transmitted.
Setup End Bit.
Hardware sets this read-only bit to 1 when a control transaction ends before software
has written 1 to the DATAEND bit. Hardware clears this bit when software writes 1 to
SSUEND.
Software should write 1 to this bit: 1) When writing 1 to INPRDY for the last outgoing
data packet. 2) When writing 1 to INPRDY for a zero-length data packet. 3) When writ-
ing 1 to SOPRDY after servicing the last incoming data packet.
This bit is automatically cleared by hardware.
Sent Stall Bit.
Hardware sets this bit to 1 after transmitting a STALL handshake signal. This flag must
be cleared by software.
IN Packet Ready Bit.
Software should write 1 to this bit after loading a data packet into the Endpoint0 FIFO
for transmit. Hardware clears this bit and generates an interrupt under either of the fol-
lowing conditions: 1) The packet is transmitted. 2) The packet is overwritten by an
incoming SETUP packet. 3) The packet is overwritten by an incoming OUT packet.
OUT Packet Ready Bit.
Hardware sets this read-only bit and generates an interrupt when a data packet has
been received. This bit is cleared only when software writes 1 to the SOPRDY bit.
SOPRDY
Description
R/W
6
0
SDSTL
R/W
5
0
Software should set this bit to 1
after servicing a Setup End (bit
SUEND) event. Hardware clears
the SUEND bit when software
writes 1 to SSUEND.
after servicing a received
Endpoint0 packet. The OPRDY bit
will be cleared by a write of 1 to
SOPRDY.
SUEND
Rev. 1.1
R
4
0
Write
DATAEND
R/W
3
0
STSTL
R/W
2
0
This bit always reads 0.
This bit always reads 0.
INPRDY
R/W
1
0
Read
OPRDY
R
0
0