C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 222

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
SFR Definition 26.1. SCON1: UART1 Control
SFR Address = 0xD2
222
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
PERR1
THRE1
Name
OVR1
REN1
RBX1
TBX1
RI1
TI1
OVR1
R/W
7
0
Receive FIFO Overrun Flag.
This bit indicates a receive FIFO overrun condition, where an incoming character is discarded
due to a full FIFO. This bit must be cleared to 0 by software.
0: Receive FIFO Overrun has not occurred.
1: Receive FIFO Overrun has occurred.
Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1 when the
parity of the oldest byte in the FIFO does not match the selected Parity Type. This bit must be
cleared to 0 by software.
0: Parity Error has not occurred.
1: Parity Error has occurred.
Transmit Holding Register Empty Flag.
0: Transmit Holding Register not Empty - do not write to SBUF1.
1: Transmit Holding Register Empty - it is safe to write to SBUF1.
Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read from the
receive FIFO.
0: UART1 reception disabled.
1: UART1 reception enabled.
Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE1 = 1. This bit is
not used when Parity is enabled.
Extra Receive Bit.
RBX1 is assigned the value of the extra bit when XBE1 = 1. If XBE1 is cleared to 0, RBX1 is
assigned the logic level of the first stop bit. This bit is not valid when Parity is enabled.
Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit. When
the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt
service routine. This bit must be cleared manually by software.
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART1 (set at the STOP bit sam-
pling time). When the UART1 interrupt is enabled, setting this bit to 1 causes the CPU to vector
to the UART1 interrupt service routine. This bit must be cleared manually by software. Note that
RI1 will remain set to '1' as long as there is still data in the UART FIFO. After the last byte has
been shifted from the FIFO to SBUF1, RI1 can be cleared.
PERR1
R/W
6
0
THRE1
R
5
1
REN1
R/W
Rev. 1.1
4
0
Function
TBX1
R/W
3
0
RBX1
R/W
2
0
R/W
TI1
1
0
R/W
RI1
0
0