C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 185

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

USB Register Definition 23.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte
USB Register Address = 0x14
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
FIFOFUL OUT FIFO Full.
DATERR Data Error Bit.
OVRUN Data Overrun Bit.
OPRDY OUT Packet Ready.
CLRDT
SDSTL
FLUSH
STSTL
Name
CLRDT
W
7
0
Clear Data Toggle Bit. Software should write 1 to
Sent Stall Bit.
Hardware sets this bit to 1 when a STALL handshake signal is transmitted. This flag
must be cleared by software.
Send Stall Bit.
Software should write 1 to this bit to generate a STALL handshake. Software should
write 0 to this bit to terminate the STALL signal. This bit has no effect in ISO mode.
FIFO Flush Bit.
Writing a 1 to this bit flushes the next packet to be read from the OUT endpoint FIFO.
The FIFO pointer is reset and the OPRDY bit is cleared. Multiple packets must be
flushed individually. Hardware resets the FLUSH bit to 0 when the flush is complete.
Note: If data for the current packet has already been read from the FIFO, the FLUSH bit should
In ISO mode, this bit is set by hardware if a received packet has a CRC or bit-stuffing
error. It is cleared when software clears OPRDY. This bit is only valid in ISO mode.
This bit is set by hardware when an incoming data packet cannot be loaded into the
OUT endpoint FIFO. This bit is only valid in ISO mode, and must be cleared by software.
0: No data overrun.
1: A data packet was lost because of a full FIFO since this flag was last cleared.
This bit indicates the contents of the OUT FIFO. If double buffering is enabled (DBIEN =
1), the FIFO is full when the FIFO contains two packets. If DBIEN = 0, the FIFO is full
when the FIFO contains one packet.
0: OUT endpoint FIFO is not full.
1: OUT endpoint FIFO is full.
Hardware sets this bit to 1 and generates an interrupt when a data packet is available.
Software should clear this bit after each data packet is unloaded from the OUT endpoint
FIFO.
STSTL
Description
R/W
not be used to flush the packet. Instead, the FIFO should be read manually.
6
0
SDSTL
R/W
5
0
C8051T620/621/320/321/322/323
this bit to reset the OUT end-
point data toggle to 0.
FLUSH
R/W
Rev. 1.1
4
0
Write
DATERR
R
3
0
OVRUN
R/W
This bit always reads 0.
2
0
FIFOFUL
Read
R
1
0
OPRDY
R/W
0
0
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