C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 164

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
23.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured
for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes
(0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see SFR Definition 23.13).
23.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for
Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN
Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for
the entire endpoint FIFO. See Table 23.3 for a list of maximum packet sizes for each FIFO configuration.
164
0x07C0
0x07BF
0x07FF
0x03FF
0x0740
0x073F
0x0640
0x063F
0x0440
0x043F
0x0400
0x0000
(1024 bytes)
User XRAM
(128 bytes)
(256 bytes)
(512 bytes)
Endpoint0
Endpoint1
Endpoint2
Endpoint3
(64 bytes)
(64 bytes)
Figure 23.3. USB FIFO Allocation
Free
Rev. 1.1
USB Clock Domain
System Clock Domain
IN, OUT, or both (Split
Configurable as
Mode)