C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 229

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt
request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the
MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the
SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-
complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into
the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer
where it can be read by the processor by reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-mas-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 27.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 27.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 27.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Figure 27.2. Multiple-Master Mode Connection Diagram
Device 1
Master
Master
Device
C8051T620/621/320/321/322/323
MISO
MOSI
MISO
MOSI
GPIO
NSS
SCK
SCK
Rev. 1.1
GPIO
MISO
MOSI
SCK
NSS
MISO
MOSI
SCK
Device 2
Master
Device
Slave
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