C8051T322-GQR Silicon Labs, C8051T322-GQR Datasheet - Page 168

• Manufacturer Part Number: C8051T322-GQR
• Description: 8-bit Microcontrollers - MCU USB-OTP-16K-LQFP32
• Manufacturer: Silicon Labs

Specifications of C8051T322-GQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051T620/621/320/321/322/323
USB Register Definition 23.8. POWER: USB0 Power
USB Register Address = 0x01
168
Name
Reset
6:5
Bit
Type
7
4
3
2
1
0
Bit
RESUME Force Resume.
USBRST Reset Detect.
USBINH USB0 Inhibit Bit.
SUSMD Suspend Mode.
Unused Unused. Read = 00b. Write = don’t care.
SUSEN Suspend Detection Enable.
ISOUD
Name
ISOUD
R/W
7
0
ISO Update Bit.
This bit affects all IN Isochronous endpoints.
0: When software writes INPRDY = 1, USB0 will send the packet when the next IN token
is received.
1: When software writes INPRDY = 1, USB0 will wait for a SOF token before sending the
packet. If an IN token is received before a SOF token, USB0 will send a zero-length data
packet.
This bit is set to 1 following a power-on reset (POR) or an asynchronous USB0 reset.
Software should clear this bit after all USB0 transceiver initialization is complete. Soft-
ware cannot set this bit to 1.
0: USB0 enabled.
1: USB0 inhibited. All USB traffic is ignored.
Writing a 1 to this bit while in Suspend mode (SUSMD = 1) forces USB0 to generate
Resume signaling on the bus (a remote wakeup event). Software should write RESUME
= 0 after 10 to 15 ms to end the Resume signaling. An interrupt is generated, and hard-
ware clears SUSMD, when software writes RESUME = 0.
Set to 1 by hardware when USB0 enters suspend mode. Cleared by hardware when soft-
ware writes RESUME = 0 (following a remote wakeup) or reads the CMINT register after
detection of Resume signaling on the bus.
0: USB0 not in suspend mode.
1: USB0 in suspend mode.
0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus.
1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend sig-
naling on the bus.
R/W
6
0
R/W
5
0
Read:
0: Reset signaling is not present.
1: Reset signaling detected on
the bus.
USBINH
R/W
Rev. 1.1
4
1
Function
USBRST
R/W
3
0
RESUME
R/W
Write:
Writing 1 to this bit forces an
asynchronous USB0 reset.
2
0
SUSMD
R
1
0
SUSEN
R/W
0
0