MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 100

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MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Overview
1.2
This section provides a high-level overview of MPC8544E features.
units within the MPC8544E.
1.2.1
The following list provides an overview of the MPC8544E feature set:
1-2
MII, GMII, TBI,
MII, GMII, TBI,
SDRAM
RTBI, RGMII,
RTBI, RGMI,
RMII, SGMII
RMII, SGMII
High-performance 32-bit e500 core that implements resources for embedded processors defined by
the Power ISA:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
— Signal-processing engine (SPE) instructions. Extensive instruction set for vector (64-bit)
— Double-precision (64-bit) floating-point instructions that use the 64-bit GPRs.
— Embedded vector and scalar single-precision (32-bit) floating-point instructions.
— 36-bit real addressing (up to 64 Gbytes of memory)
— Memory management unit (MMU) especially designed for embedded applications that support
Flash
GPIO
IRQs
DDR
Serial
MPC8544E Overview
be locked entirely or on a per-line basis, with separate locking for instructions and data.
integer and fractional operations. These instructions use both the upper and lower words of the
64-bit general-purpose registers (GPR) as they are defined by the SPE category of the Power
ISA.
4-Kbyte–4-Gbyte page sizes.
I
I
Key Features
2
2
C
C
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Programmable Interrupt
Local Bus Controller
Memory Controller
Controller (PIC)
DDR/DDR2/
Controller
Controller
10/100/1Gb
10/100/1Gb
DUART
eTSEC
eTSEC
I
I
2
2
C
C
Figure 1-1. MPC8544E Block Diagram
Coherency
OceaN
Switch
Fabric
Security
Module
Engine
Engine
e500
XOR
Core Complex
256-Kbyte
L2 Cache/
32-bit PCI Bus Interface
SRAM
Figure 1-1
Bus
4-Channel DMA
PCI Express
Interfaces
Controller
32-Kbyte L1
Instruction
shows the major functional
Cache
e500 Core
Freescale Semiconductor
32-Kbyte
L1 Data
Cache
PCI 32-bit
66 MHz
dual x4 and
single x1
External
Control

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