MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 648

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local Bus Controller
Table 14-19
14-28
11–15
11–15
16–19
20–27
28–29
4–10
Bits
0–2
3
SRCID Captures the source of the transaction when this information is provided on the internal interface to the LBC.
SRCID Captures the source of the transaction when this information is provided on the internal interface to the LBC.
Name
RWB
BNK
PB
XA
—
—
describes LTEATR fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Transaction type for the error
0 The transaction for the error was a write transaction.
1 The transaction for the error was a read transaction.
Reserved
00000 PCI1/PCI-X interface
00001 PCI2 interface
00010 PCI Express
00011 Reserved
00100 Local Bus
00101–00111 Reserved
01000 Configuration space
01001 Reserved
01010 Boot sequencer
01011 Reserved
01100 Serial RapidIO
01101–01110 Reserved
01111 DDR controller
10000 Processor (instruction)
10001 Processor (data)
00000 PCI interface
00001 PCI Express interface 2
00010 PCI Express interface 1
00011 PCI Express interface 3
00100 Local Bus
00101–00111 Reserved
01000 Configuration space
01001 Reserved
01010 Boot sequencer
01011–01110 Reserved
01111 DDR controller
10000 Processor (instruction)
10001 Processor (data)
Parity error on byte. There are four parity error status bits, one per byte lane. A bit is set for the byte that had
a parity error (bit 16 represents byte 0, the most significant byte lane).
Memory controller bank. There is one error status bit per memory controller bank (bit 20 represents bank 0).
A bit is set for the local bus memory controller bank that had an error. Note that BNK is invalid if the error was
not caused by parity checks.
Extended address for the error. These bits capture the two msbs of the 34-bit address of the transaction
resulting in an error.
Table 14-19. LTEATR Field Descriptions
Description
10010 Reserved
10011 Reserved
10100 Reserved
10101 DMA
10110 Reserved
10111 SAP
11000 eTSEC 1
11001 eTSEC 2
11010 eTSEC 3
11011 eTSEC 4
11100 RapidIO Message Unit
11101 RapidIO Doorbell Unit
11110 RapidIO Port-write Unit
11111
10010 Reserved
10011 Reserved
10100 Reserved
10101 DMA
10110 Reserved
10111 SAP
11000 eTSEC 1
11001 Reserved
11010 eTSEC 3
11011 Reserved
11100 Reserved
11101 Reserved
11110 Reserved
11111
Reserved
Reserved
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