MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 432

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
10.3.4.3
Figure 10-27
Table 10-30
10.3.5
Writing to one of the four message registers (MSGR0–MSGR3) causes a messaging interrupt to the
processor. Reading this register clears the messaging interrupt. Note that a messaging interrupt can also be
cleared by writing a one to the corresponding status field of the PIC message status register (MSR), shown
in
10.3.5.1
The message registers (MSGR0–MSGR3), shown in
Table 10-32
10-34
Offset PM0MR2: 0x4_1364, PM1MR2: 0x4_1384, PM2MR2: 0x4_13A4, PM3MR2: 0x4_13C4
Reset 1
16–31
0–15
0–31
Offset MSGR0: 0x4_1400, MSGR1: 0x4_1410, MSGR2: 0x4_1420, MSGR3: 0x4_1430
Bits
Reset
Bits
Figure
W
R
W
R
0
0
Name
Name
MSG
10-30.
INT
1
—
describes the PMnMR2 fields.
describes the MSGR registers.
1
Message Registers
shows the PM0MR2, PM1MR2, PM2MR2, and PM3MR2 registers.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Performance Monitor n Mask Registers 2 (PM n MR2)
Message Registers (MSGR0–MSGR3)
Internal interrupts 32–48
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
Reserved, should be cleared.
Message. Contains the 32-bit message data.
1
1
Figure 10-27. Performance Monitor n Mask Registers 2 (PM n MR2)
1
1
1
INT
1
Figure 10-28. Message Registers (MSGRs)
Table 10-31. PM n MR2 Field Descriptions
Table 10-32. MSGR n Field Descriptions
1
1
1
1
1
1
All zeros
15 16
Figure
1
MSG
Description
Description
0
0
10-28, contain a 32-bit message.
0
0
0
0
0
0
—
0
Freescale Semiconductor
0
Access: Read/Write
0
Access: Read/Write
0
0
0
0
31
31
0