MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 200

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Complex Overview
If a branch resolves as correct, instructions in the target stream are marked nonspeculative and are allowed
to complete. If the branch history bits in the BTB indicated weakly taken or weakly not taken, the
prediction is upgraded to strongly taken or strongly not taken.
If a branch resolves as incorrect, instructions in the target stream are flushed from the execution pipeline, the
branch history bits are updated in the BTB entry, and nonspeculative fetching begins from the correct path.
5.5.3
The seven stages of the e500 execution pipeline—fetch1, fetch2/predecode, decode/dispatch, issue,
execute, complete, and write back—are highlighted in grey in
The common pipeline stages are as follows:
5-14
•
Instruction fetch—Includes the clock cycles necessary to request an instruction and the time the
memory system takes to respond to the request. Instructions retrieved are latched into the instruction
queue (IQ) for subsequent consideration by the dispatcher.
At dispatch, instructions are deallocated from the
IQ and assigned sequential positions in the CQ.
e500 Execution Pipeline
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Branch Issue Queue (BIQ)
Indicates stages
Execute
Finish
BU
BU
LSU Stage 1
Stage 2
Stage 3
Figure 5-5. Instruction Pipeline Flow
Execute Stage
Issue Stage
Completion Stage
Write-Back Stage
MU Stage 1
Stage 2
Stage 3
Stage 4
General Issue Queue (GIQ)
Fetch Stage 1
Fetch Stage 2
Decode Stage
Divide Bypass
Postdivide
Divide
Maximum two-instruction
completion per clock cycle
Maximum two-instruction per cycle dispatch
to the issue queues. BIQ can accept one
per cycle; GIQ can accept at most two.
Figure
5-5.
Maximum four-instruction
fetch per clock cycle
Instruction Cache
SU1
Freescale Semiconductor
SU2