MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 292

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM

condition exists, the L2 signals an interrupt to the core through the internal int signal.

Offset 0x2_0E44

Offset 0x2_0E48

MBECCDIS Multiple-bit ECC error disable. Note that uncorrectable read errors may cause the assertion of

SBECCDIS Single-bit ECC error disable

describes L2ERRDIS fields.

shows the L2 error disable register (L2ERRDIS).

shows the L2 error interrupt enable register (L2ERRINTEN). When an enabled error

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Tag parity error disable

0 Tag parity error detection enabled

1 Tag parity error detection disabled

core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and this error occurs, MBECCDIS must be cleared and

L2ERRINTEN[MBECCINTEN] must be set to ensure that an interrupt is generated. For more information,

0 Multiple-bit ECC error detection enabled

1 Multiple-bit ECC error detection disabled

0 Single-bit ECC error detection enabled

1 Single-bit ECC error detection disabled

L2 configuration error disable

0 L2 configuration error detection enabled

1 L2 configuration error detection disabled

Section 6.10.2, “Hardware Implementation-Dependent Register 1

Figure 7-21. L2 Error Interrupt Enable Register (L2ERRINTEN)

Figure 7-20. L2 Error Disable Register (L2ERRDIS)

Table 7-17. L2ERRDIS Field Descriptions

TPARINTEN MBECCINTEN SBECCINTEN

TPARDIS MBECCDIS0 SBECCDIS — L2CFGDIS

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Access: Read/Write