MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 165

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-7
4.3.1.3
When the e500 core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. The
core begins execution with the instruction at effective address 0x0_FFFF_FFFC. To get this instruction,
the core’s first instruction fetch is a burst read of boot code from effective address 0x0_FFFF_FFE0. For
systems in which the boot code resides at a different address, the MPC8544E provides boot page
translation capability. Boot page translation is controlled by the boot page translation register (BPTR).
The boot sequencer can enable boot page translation, or the boot page translation can be set up by an
external host when the MPC8544E is configured to be in boot holdoff mode. If translation is to be
performed to a page outside the default boot ROM address range defined in the MPC8544E (8 Mbytes at
0x0_FF80_0000 to 0x0_FFFF_FFFF as defined in
host or boot sequencer must then also set up a local access window to define the routing of the boot code
fetch to the target interface that contains the boot code, because the BPTR defines only the address
translation, not the target interface. See
Section 11.4.5, “Boot Sequencer Mode,”
4.3.1.3.1
Figure 4-4
Freescale Semiconductor
12–31
8–11
Bits
1–7
Offset 0x0_0020
Reset
0
W
R
TRGT_ID
EN
0
defines ALTCAR fields.
Name
shows the fields of BPTR.
EN
—
—
1
Boot Page Translation
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Boot Page Translation Register (BPTR)
Enable for a second configuration window. Like CCSRBAR, it has a fixed size of 1 Mbyte.
0 Second configuration window is disabled.
1 Second configuration window is enabled.
Write reserved, read = 0
Identifies the device ID to target when a transaction hits in the 1-Mbyte address range defined by the
second configuration window.
0000 PCI Interface
0001 PCI Express 2
0010 PCI Express 1
0011 PCI Express 3
0100 Local bus controller
0101–1011Reserved
1000 Configuration, control, status registers
Write reserved, read = 0
—
Figure 4-4. Boot Page Translation Register (BPTR)
7
8
Table 4-7. ALTCAR Bit Settings
Section 2.1, “Local Memory Map Overview and Example,”
for more information.
Section 4.4.3.4, “Boot ROM
All zeros
Description
1001–1010 Reserved
1011 Security
1100 Reserved
1101 Reserved
1110 Reserved
1111 Local memory —DDR SDRAM and on-chip
BOOT_PAGE
SRAM
Reset, Clocking, and Initialization
Location”), the external
Access: Read/Write
and
4-7
31