MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 208

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Complex Overview
5.9
The e500 core complex supports demand-paged virtual memory as well other memory management
schemes that depend on precise control of effective-to-physical address translation and flexible memory
protection as defined by the architecture. The mapping mechanism consists of software-managed TLBs
that support variable-sized pages with per-page properties and permissions. The following properties can
be configured for each TLB:
The core complex employs a two-level memory management unit (MMU) architecture. There are separate
instruction and data level-1 (L1) MMUs backed up by a unified level-2 (L2) MMU.
5-22
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User-mode page execute access
User-mode page read access
User-mode page write access
Supervisor-mode page execute access
Supervisor-mode page read access
Supervisor-mode page write access
Write-through required (W)
Caching inhibited (I)
Memory coherency required (M) (the M bit has no effect on the MPC8544E). See
(feature “Multiprocessor functionality”) for further details.
Guarded (G)
Endianness (E)
User-definable (U0–U3), a 4-bit implementation-specific field
Memory Management
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 5-7. Interrupt Vector Registers and Exception Conditions (continued)
Register
IVOR14
IVOR15
IVOR32
IVOR33
IVOR34
IVOR35
Instruction TLB error interrupt offset
Debug interrupt offset
SPE unavailable interrupt offset
SPE floating-point data exception interrupt offset
SPE floating-point round exception interrupt offset
Performance monitor
e500-Specific IVORs
Interrupt
Freescale Semiconductor
Table 5-8