MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 861

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6.1.3
This section describes the gigabit media-independent interface (GMII) intended to be used between the
PHYs and the eTSEC.
required to establish the eTSEC module connection with a PHY.
A GMII interface has 28 signals (TSECn_GTX_CLK + _GTX_CLK125 included), as defined by the IEEE
802.3u standard, for connecting to an Ethernet PHY.
15.6.1.4
This section describes the reduced gigabit media-independent interface (RGMII) intended to be used
between the PHYs and the GMII MAC. The RGMII is an alternative to the IEEE802.3u MII, the
IEEE802.3z GMII and the TBI. The RGMII reduces the number of signals required to interconnect the
MAC and the PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost
effective and technology independent manner. To accomplish this objective, the data paths and all
associated control signals are multiplexed using both edges of the clock. For gigabit operation, the clocks
operate at 125MHz, and for 10/100 operation, the clocks operate at 2.5 MHz or 25 MHz, respectively. Note
that the GTX_CLK125 input must be provided at 125 MHz for an RGMII interface, regardless of operation
speed (1 Gbps, 100 Mbps, or 10 Mbps).
media-independent interface and the signals required to establish the gigabit Ethernet controllers’ module
connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a
9/22/00.
Freescale Semiconductor
2
The management signals (MDC and MDIO) are common to all of the Ethernet controllers module
connections in the system, assuming that each PHY has a different management address.
eTSEC
Gigabit Media-Independent Interface (GMII)
Reduced Gigabit Media-Independent Interface (RGMII)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 14-185
Reference Clock (TSEC n _TX_CLK)
Receive Control (RX_DV, RX_ER)
Figure 15-118. eTSEC-RMII Connection
Transmit Data (TSEC n _TXD[1:0])
Receive Data (TSEC n _RXD[1:0])
Management Data Clock
Management Data I/O
Transmit Control (TX_EN)
depicts the basic components of the GMII including the signals
Figure 15-119
2
(MDIO)
depicts the basic components of the gigabit reduced
2
(MDC)
Enhanced Three-Speed Ethernet Controllers
Ethernet
RMII
PHY
Medium
15-129