MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1255

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21-25
21.4
The debug features on the MPC8544E use the LBC interfaces, and the DDR SDRAM interface.
21.4.1
Debug information that is common to all the interfaces is the source ID (SID). The transaction source ID
provides enough information to determine which block or port originated a transaction including the
distinction between instruction and data fetches from the processor core.
interpretation for the 5-bit SID field. Note that the table also includes ports that are only slaves, such as
local memory. These ports are always targets. As such, the value shown represents a target ID (TID) and
not a source ID. For ports that can function in both capacities, the value indicates source ID when
mastering transactions, and target ID when responding as slave. The TID field is only meaningful when
one of the following participates in the transaction:
Freescale Semiconductor
8–31
Bits
0–4
5–7
•
•
•
(Hex)
Value
The e500 coherency module (ECM) dispatch bus
The watchpoint monitor (WMCR1[IFSEL] = 000)
The trace buffer (TBCR1[IFSEL] = 000)
00
01
02
03
04
05
Name
SEL
Functional Description
—
—
Source and Target ID
describes the TOSR fields.
PCI
PCI Express 2
PCI Express 1
PCI Express 3
Local bus controller
Reserved
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Select. Selects the source for TRIG_OUT
000 READY signal. Multiplexed with TRIG_OUT. Basic device state indicator. READY asserts whenever the
001 Selects the watchpoint monitor hit indication
010 Selects the trace buffer hit indication
011 Selects the performance monitor overflow indication
Reserved
device is not in reset or not asleep. See
about the reset sequence, and
management states.
Source (or Target) Port
Table 21-26. Source and Target ID Values
Table 21-25. TOSR Field Descriptions
Chapter 19, “Global Utilities,”
(Hex)
Value
Chapter 4, “Reset, Clocking, and Initialization,”
14
15
10
11
12
13
Description
Local processor (instruction fetch)
Local processor (data fetch)
Reserved
Reserved
Reserved
DMA
Source (or Target) Port
for more information about power
Table 21-26
Debug Features and Watchpoint Facility
shows the values and
for more details
21-25